Staff Engineer, Design Verification
4 weeks ago
About Analog Devices
Analog Devices, Inc. (NASDAQ:) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible. Learn more atand onand.
Job Description
- Own and deliver on design verification of complex Intellectual Property (IP) or Subsystem orcomplete full chip (SoC)level features and mixed signal subsystems.
- Collaborate with design, applications, product and test engineering teams to ensure the implementation meets both architectural and micro-architectural intent for complex IPs and feature areas of subsystem and SoC.
- Develop test methodologies, strategies, reviews and supervise execution of test plans.
- Develop verification environments involving directed, formal, constrained random stimulus and coverage driven verification run and debug simulations to drive quality.
- Execute test plans for complex design areas or products by leveraging teams, as well as through individual contributions. Set targets for test coverage and strategy to achieve coverage. Ensure quality of test plan execution across broad areas.
- Apply Agile development methodologies including code reviews, sprint planning, and feature deployment.
- Innovate to improve verification efficiency through methodologies, processes or tools.
- Provide technical leadership through coaching, mentorship, modeling and teamwork.
- Demonstrate ADI core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact and Diversity & Inclusion.
Minimum Qualifications
- Bachelors or masters degree, in Engineering (Electronic Engineering) or equivalent
- Excellentdebugging and analytical skills.
- 10 12 years in ASIC design verification.
Additional Qualifications & Experience:
- Verification Planning tools (ePlanner, vManager)
- Property Specification Language (PSL), SystemVerilog Assertions (SVA)
- Proficient with Cadence Suite (Virtuoso IUS)
- Scripting languages (Shell, TCL, PERL, Python) for bench automation
- Hands-On UVM at user level, pseudo and constrained random techniques, assertion-based verification techniques with System Verilog.
- Debugging of Gate Level Simulation (GLS), waiving Timing Violations approved by designer.
- Coding up in C tests on M3 Series Cortex based products.
- Building and leading small verification teams. Strong interpersonal, teamwork and communication skills are required. Be self-motivated and enthusiastic. Strong level of English speaking and writing.
Job Req Type: Experienced
Required Travel: Yes, 10% of the time
Shift Type: 1st Shift/Days
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