Senior ASIC Verification Engineer at Sykatiya Technology Pvt Ltd
3 weeks ago
Job Overview :
We are seeking a highly skilled Senior ASIC Verification Engineer to join our team at Sykatiya Technology Pvt Ltd. In this role, you will be responsible for designing and implementing verification environments for complex ASICs using System Verilog and UVM methodology.
Main Responsibilities :
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Expose our engineers to the latest verification methodologies, including UVM, to enable complex feature verification suites.
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Architect and develop block-level verification environments for sub-systems and full-chip using System Verilog and UVM methodology.
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Define, architect, code, and deliver verification suites/tests for ASICs that enable faster, denser, feature-rich systems using various front-end simulator tools (VCS/NC).
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Verify large ASIC blocks independently and rapidly, and sign off on them for tape-out with analysis of code coverage, functional coverage, and gate-level simulation.
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Develop Perl, Python, and/or shell scripts to improve our current verification infrastructure/methodology.
Requirements :
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4+ years of experience in real-time projects.
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Strong experience in ASIC verification using System Verilog.
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Experience with verification methodologies like OVM/VMM/UVM is a strong plus.
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Perl/Tcl scripting skills are highly preferred.
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Strong problem-solving and ASIC debugging skills.
Education Background :
B.E./B.S./B.Tech/M.S./M.Tech in Engineering.
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