Senior Verification Engineer
1 month ago
We are seeking a highly skilled and experienced Verification Engineer to join our team at Sykatiya Technologies. As a key member of our verification team, you will be responsible for planning, verifying, and ensuring coverage closures of RTL designs, primarily focusing on Ethernet and SerDes interfaces using the UVM methodology.
Key Responsibilities:
- Plan and execute verification strategies for RTL designs
- Develop and maintain functional coverage based constrained random verification environments
- Expertise in block, sub-system, and top-level verification
- Experience with DV methodologies like UVM/VMM and industry-standard verification tools for simulation and debug
- Integration and working with C-reference models in SV test benches
- Scripting skills in Perl, Python, or Shell
- Gate level simulations with SDF annotation
- Knowledge of IEEE 802.3 Physical layer clauses
- Experience with high-speed SerDes IP verification is a plus
- Understanding of PLLs, CDR concepts, AMS interfaces, and networking IP designs is a plus
About Us:
Sykatiya Technologies is a leading provider of VLSI Design, Test Services, and Specialized Solutions. We pride ourselves on our technical expertise and customer-centric approach. Our team comprises highly talented engineers and experts in Design Verification, DFT/Test, Physical Design, and Analog Design for ASICs. We strive to bring value-adds to our customers' projects, helping them save dollars and stay ahead of the competition.
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