Senior ASIC Physical Design Engineer at Sykatiya Technologies
3 weeks ago
Key Responsibilities:
As a Senior ASIC Physical Design Engineer at Sykatiya Technologies, you will be responsible for designing and developing complex ASICs using advanced low power techniques and cutting-edge design tools. Your expertise in Cadence or Synopsys tools is crucial for floor planning, P&R, extraction, IR Drop Analysis, Timing, and Signal Integrity closure, Physical Verification, and Static Timing Analysis.
Essential Skills:
- Experience with 7nm node and advanced low power techniques
- Proficiency in Cadence or Synopsys tools, especially Cadence Innovus
- Hands-on experience with Perl, TCL, and Primetime or Primetime-SI
- Strong problem-solving skills and knowledge of ASIC fundamentals
- Excellent timing closure skills for high-speed interfaces
Bonus Skills:
- Experience with Full chip Physical Design
- Knowledge of advanced ASIC design techniques
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