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1 week ago
Our ideal candidate will be responsible for creating memory compilers and Fast Cache instances that achieve exceptional Performance, Power, and Area (PPA) for our next-generation Cores.
- We are seeking a Senior Memory Design Engineer to join our team who has expertise in developing high-performance memory compilers and can understand complex computer architecture concepts.
- The successful candidate will have hands-on experience with CMOS Transistors, high-speed/low-power CMOS circuit design, clocking schemes, Static and complex logic circuits.
- They should possess a deep understanding of Power versus Performance versus Area trade-offs in typical CMOS design and be able to apply this knowledge effectively.
- In addition, the ideal candidate will work collaboratively as part of a team, possessing excellent interpersonal skills to drive goals forward.
- Key responsibilities include ensuring SRAM/margin, char, and quality checks meet expectations.
Nice to Have Skills and Experience:
- Basic scripting languages, e.g., Perl/TCL/Python, would be beneficial for this role.
- Familiarity with working on Cadence or Synopsys flows is highly desirable.
- Circuit Simulation and Optimization of standard cells are also essential skills for this position.
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