
Senior Testbench Expert
18 hours ago
We are seeking a highly skilled Senior Design Verification Engineer to join our team. The ideal candidate will have extensive experience in design verification with a strong focus on complex test-bench/models and possess excellent communication skills.
In this role, you will be responsible for working on complex test-bench/models in Verilog, System Verilog, or SystemC and developing and implementing verification flows using OVM/UVM methodology. You will also collaborate with cross-functional teams to identify and resolve technical issues and perform SOC/IP performance verification and debug.
To succeed in this position, you should have a solid understanding of programming languages such as C/C++, PERL/Shell script, and assembly language. Experience in architecture domains such as x86 or ARM is preferred. Additionally, background in SOC/IP performance verification is highly desirable.
Key Responsibilities:
- Work on complex test-bench/models in Verilog, System Verilog, or SystemC.
- Develop and implement verification flows using OVM/UVM methodology.
- Collaborate with cross-functional teams to identify and resolve technical issues.
- Perform SOC/IP performance verification and debug.
Preferred Qualifications:
- Experience in architecture domains such as x86 or ARM.
- Background in SOC/IP performance verification.
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