
Senior Testbench Developer
11 hours ago
Job Title: Design Verification Engineer
Description:
We are looking for a skilled and experienced Design Verification Engineer to join our team. In this role, you will be responsible for creating UVM testbenches for a System-on-Chip (SoC) and Intellectual Property (IP), as well as tests, regressions, and functional coverage to achieve zero bug escapes.
You will work closely with designers to develop test plans and create testcases and coverage to thoroughly verify the Register Transfer Level (RTL). As a key member of the team, you will be responsible for designing, developing, and maintaining modular and reusable UVM testbenches for blocks.
You will collaborate with colleagues to develop test plans and create randomized tests, adding constraints and directed tests to fully cover functionality. You will confirm test completeness through code and functional coverage and review testbenches, tests, and coverage with designers, architects, and software engineers.
In addition, you will integrate tests and coverage within the full environment and write C-based BareMetal code for SoC level verification. Relevant experience of 3-10 years is required.
Key Responsibilities:
- Create UVM testbenches, tests, and constraints to ensure design correctness
- Design, develop, and maintain modular and reusable UVM testbenches for blocks
- Collaborate with colleagues to develop test plans
- Create randomized tests, adding constraints and directed tests to fully cover functionality
- Confirm test completeness through code and functional coverage
- Review testbenches, tests, and coverage with designers, architects, and SW engineers
- Integrate tests and coverage within full environment
- Write C-based BareMetal code for SoC level verification
Requirements:
Relevant experience of 3-10 years
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