Highly Skilled RTL Design and Verification Engineer
5 days ago
We are seeking an experienced RTL Design and Verification Engineer to join our team at UST.
About the Role:
The successful candidate will have a strong background in digital logic design, Verilog/RTL design, and IP block architecture. You will be responsible for designing and verifying complex digital circuits, as well as working with simulation tools such as Synopsys/Cadence/Mentor.
Key Responsibilities:
- Design and verify digital circuits using Verilog and RTL design methodologies.
- Develop and maintain documentation of design and verification activities.
- Collaborate with cross-functional teams to integrate designs into larger systems.
- Identify and troubleshoot issues in designs and verification results.
Requirements:
To be successful in this role, you will need:
- A minimum of 7 years of experience in digital logic design, Verilog/RTL design, and IP block architecture.
- Expertise in simulation tools such as Synopsys/Cadence/Mentor.
- Strong understanding of digital logic design concepts, including flip-flops, counters, and multiplexers.
- Experience with Perl/TCL scripting and automation is desirable.
- Knowledge of RTL logic synthesis, sdc, and constraint writing is also desirable.
Benefits:
We offer a competitive salary package, including:
- A base salary of $120,000 per year.
- Opportunities for professional growth and development.
- A collaborative and dynamic work environment.
How to Apply:
If you are a motivated and experienced engineer looking for a new challenge, please submit your resume and cover letter for consideration.
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