Senior Staff RTL Design Engineer

7 days ago


Noida, Uttar Pradesh, India Synopsys Inc Full time
Job Description and Requirements

The System Solutions Group at Synopsys Inc is seeking a highly experienced RTL Design Engineer to join our team. As an expert in RTL Signoff and Design, you will be responsible for delivering high-quality designs and signoffs for complex SoCs.

In this role, you can expect to work on a wide range of activities including Lint/CDC/RDC checks, timing constraints development, preliminary synthesis, formality, and RTL design. You will also have the opportunity to work with cutting-edge technologies deployed for RTL Quality Signoff for Semiconductors.

Responsibilities:
  • Collaborate with Synopsys customers to understand their needs and define RTL Signoff and design scope and activities.
  • Understand the complexity and requirements of RTL Quality Signoff and propose resource requirements to complete the activities.
  • Lead teams of engineers to perform various pre-silicon static verification activities on IPs/Subsystems.
  • Develop and lead the team to create timing constraints for synthesis and timing.
  • Work with peers to improve methodology and execution efficiency.
  • Ramp-up on new RTL Design and Static Verification tools and methodologies using Synopsys Products to enable customers.
  • Work with other Synopsys teams including BU AEs and Sales to develop, broaden, and deploy Tool and IP solutions.
  • Setup flows and methodologies to enable quick setup for RTL Quality checks, Synthesis, and Formality.
  • Train teams in design concepts and root-cause analysis.
Requirements

We are looking for candidates with the following qualifications:

  • B.E/B.Tech/M.E/M.Tech in Electronics with a minimum of 8+ years' experience in RTL Design and Verification.
  • Technical expertise in various aspects of RTL Design and Signoff: LINT, CDC, RDC.
  • Technical expertise on setting up flows and methodologies for quick deployment of RTL Signoff tools.
  • Technical expertise in debugging and diagnosing violations and errors.
  • Technical expertise in developing timing constraints and running preliminary synthesis for timing constraints check and area estimation.
  • Ability to lead teams to perform RTL Signoff on complex SoC/IP/Subsystem.
  • Experience with planning and managing various activities related to RTL Signoff and Design.
  • Strong understanding of design concepts, ASIC flows, and stakeholders.
  • Good communication skills.
About Us

Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.



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