Physical Verification Engineer

Physical Verification Engineers Experience : 2-5 years Location : Bangalore Job Description – Physical Verification Engineer Key Responsibilities Perform physical verification for SoCs, cores, and block-level designs. Run and debug DRC (Design Rule Check), LVS (Layout vs. Schematic), ERC (Electrical Rule Check), Antenna checks, and DFM (Design for...

Physical Verification Engineer Job Description Work with various implementation team to drive full-chip Physical Verification Sign-off closure in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out. Co-work with Place & Route team to resolve full-chip layout integration issues. Work with various implementation team to drive Physical Verification...

Physical Verification EngineerJob DescriptionWork with various implementation team to drive full-chip Physical Verification Sign-off closure in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out.Co-work with Place & Route team to resolve full-chip layout integration issues.Work with various implementation team to drive Physical VerificationCoordinates...

Physical Verification Engineers Experience : 3 years Location : Bangalore Will be responsible for Runing Physical verification analysis for multiple designs, analyzing results and providing fixes to address the issues for complex cpu designs, in latest technology nodes. n (LVS, DRC, ERC, PERC, Antenna, DFM) at block and top levels. Collaborate with Physical...

Physical Verification Engineer Experience: 2 to 5 Years Location: Bangalore Notice Period: Immediate Job Description Key Responsibilities: Perform Physical Verification checks including DRC, LVS, ERC , and Antenna checks at block and full-chip level . Work with foundry rule decks (TSMC / Samsung / GF / Intel / UMC etc.) to ensure design sign-off compliance....

Physical Verification EngineersExperience : 2-5 yearsLocation : BangaloreJob Description – Physical Verification EngineerKey ResponsibilitiesPerform physical verification for SoCs, cores, and block-level designs.Run and debug DRC (Design Rule Check), LVS (Layout vs. Schematic), ERC (Electrical Rule Check), Antenna checks, and DFM (Design for...

Experience of 5+ years in Physical verification and closure. Location: Bangalore NP - Immediate Main responsibility of the candidate will be around achieving a clean GDS view with below key items: Physical Verification closure for Arm CPU implementation: Should have completed multiple tape-outs with Physical Verification closure role in the past Strong...

Experience of 5+ years in Physical verification and closure. Location: BangaloreNP - ImmediateMain responsibility of the candidate will be around achieving a clean GDS view with below key items:Physical Verification closure for Arm CPU implementation:Should have completed multiple tape-outs with Physical Verification closure role in the pastStrong...

Job Summary We are seeking a highly experienced Senior Physical Design Engineer with a minimum of 10 years in the RTL to GDSII flow. This role requires hands-on expertise with Cadence Innovus , experience at N3 and below process nodes , and strong scripting and flow debugging skills . Key Responsibilities Lead physical design activities from RTL to GDSII,...

Company Description Tranzium Semi Private Limited is a leading innovator in the semiconductor and software industry, dedicated to delivering high-performance, power-efficient chips for multinational technology leaders worldwide. Our vision is to be at the forefront of technological innovation, driving the advancement of tomorrow's most advanced technologies....