Senior Design-for-Debug Verification Engineer
5 days ago
Job ResponsibilityPre-silicon system verification. This include SoC, FPGA & Full Chip design verification.Create testcase and testbench with UVM methodologyFullchip/system functional verification, by defining verification strategies/methodology and test plan to enable effective verificationCoordinate/interface cross functional efforts with Design, SW, Architecture team to achieve full coverage verification planExperience on Emulation will be an add on.Qualifications:6+ years of experience with complex ASIC designs and/or verificationFamiliar with System Verilog languageExperience on UVM verification methodology, and formal verification methodWorking knowledge of scripting in Linux/ Unix environments as well as proficiency in Perl and or Python is desirable.Experience with Design for Debug (JTAG, High speed USB, PCIe based debug, Visualization of Internal Signal) architecture and design verification of same.Experience with ARM and RISC Debug Architectures is desired with focus on design verification.Any prior working experience on UltraSoC/ Tessent Embedded Analytics Debug Architecture will be a plus but not must for this position.Strong communication skills and the ability to work with a team spread across different geography sitesFlexible in dynamic environment
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Senior Design Verification Engineer
6 days ago
Bangalore, India UST Full timeJob Description: As a Sr. SoC Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable...
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Senior Design Verification Engineer
5 days ago
bangalore, India UST Full timeJob Description:As a Sr. SoC Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable...
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Bangalore, India UST Full timeJob Responsibility Pre-silicon system verification. This include SoC, FPGA & Full Chip design verification. Create testcase and testbench with UVM methodology Fullchip/system functional verification, by defining verification strategies/methodology and test plan to enable effective verification Coordinate/interface cross functional efforts with Design, SW,...
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Senior Design Verification Engineer
5 days ago
Bangalore Urban, India UST Full timeJob Description: As a Sr. SoC Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable...
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Senior Design Verification Engineer
5 days ago
Bangalore Urban, India UST Full timeJob Description:As a Sr. SoC Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable...
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Bangalore Urban, India UST Full timeJob Responsibility Pre-silicon system verification. This include SoC, FPGA & Full Chip design verification. Create testcase and testbench with UVM methodology Fullchip/system functional verification, by defining verification strategies/methodology and test plan to enable effective verification Coordinate/interface cross functional efforts with Design, SW,...
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Bangalore Urban, India UST Full timeJob ResponsibilityPre-silicon system verification. This include SoC, FPGA & Full Chip design verification.Create testcase and testbench with UVM methodologyFullchip/system functional verification, by defining verification strategies/methodology and test plan to enable effective verificationCoordinate/interface cross functional efforts with Design, SW,...
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Bangalore, India UST Full timeJob Description: As a Sr. SoC Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable...
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Bangalore, India UST Full timeJob Responsibility - Pre-silicon system verification. This include SoC, FPGA & Full Chip design verification. - Create testcase and testbench with UVM methodology - Fullchip/system functional verification, by defining verification strategies/methodology and test plan to enable effective verification - Coordinate/interface cross functional efforts with...
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bangalore district, India Tenstorrent Full timeTenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high...
