Senior Design-for-Debug Verification Engineer
5 days ago
Job ResponsibilityPre-silicon system verification. This include SoC, FPGA & Full Chip design verification.Create testcase and testbench with UVM methodologyFullchip/system functional verification, by defining verification strategies/methodology and test plan to enable effective verificationCoordinate/interface cross functional efforts with Design, SW, Architecture team to achieve full coverage verification planExperience on Emulation will be an add on.Qualifications:6+ years of experience with complex ASIC designs and/or verificationFamiliar with System Verilog languageExperience on UVM verification methodology, and formal verification methodWorking knowledge of scripting in Linux/ Unix environments as well as proficiency in Perl and or Python is desirable.Experience with Design for Debug (JTAG, High speed USB, PCIe based debug, Visualization of Internal Signal) architecture and design verification of same.Experience with ARM and RISC Debug Architectures is desired with focus on design verification.Any prior working experience on UltraSoC/ Tessent Embedded Analytics Debug Architecture will be a plus but not must for this position.Strong communication skills and the ability to work with a team spread across different geography sitesFlexible in dynamic environment
-
Senior Design Verification Engineer
5 days ago
Bangalore Urban, India UST Full timeJob Description: As a Sr. SoC Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable...
-
Senior Design Verification Engineer
5 days ago
Bangalore Urban, India UST Full timeJob Description:As a Sr. SoC Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable...
-
Bangalore Urban, India UST Full timeJob Responsibility Pre-silicon system verification. This include SoC, FPGA & Full Chip design verification. Create testcase and testbench with UVM methodology Fullchip/system functional verification, by defining verification strategies/methodology and test plan to enable effective verification Coordinate/interface cross functional efforts with Design, SW,...
-
Senior Design Verification Engineer
6 days ago
Bangalore, India UST Full timeJob Description: As a Sr. SoC Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable...
-
Senior Design Verification Engineer
5 days ago
bangalore, India UST Full timeJob Description:As a Sr. SoC Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable...
-
Bangalore, India UST Full timeJob Responsibility Pre-silicon system verification. This include SoC, FPGA & Full Chip design verification. Create testcase and testbench with UVM methodology Fullchip/system functional verification, by defining verification strategies/methodology and test plan to enable effective verification Coordinate/interface cross functional efforts with Design, SW,...
-
bangalore, India UST Full timeJob ResponsibilityPre-silicon system verification. This include SoC, FPGA & Full Chip design verification.Create testcase and testbench with UVM methodologyFullchip/system functional verification, by defining verification strategies/methodology and test plan to enable effective verificationCoordinate/interface cross functional efforts with Design, SW,...
-
Senior Design Verification Engineer
1 week ago
Bangalore Urban, India L&T Technology Services Full timeSoC/SS Lead Engineers : Experience in development of UVM based verification environments from scratch. Experience with Design verification of ta-center applications like Video, AI/ML and Networking designs. Experience in Mercurial (Hg), Git or SVN. Experience with low power design. Experience working across and building relationships with cross-functional...
-
Senior Design Verification Engineer
3 weeks ago
Bangalore Urban, India L&T Technology Services Full timeSoC/SS Lead Engineers : Experience in development of UVM based verification environments from scratch. Experience with Design verification of ta-center applications like Video, AI/ML and Networking designs. Experience in Mercurial (Hg), Git or SVN. Experience with low power design. Experience working across and building relationships with cross-functional...
-
Bangalore, India UST Full timeJob Description: As a Sr. SoC Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable...
