ASIC Test Engineer

ASIC Design Engineer We are seeking a skilled ASIC Design Engineer with a solid background in digital design , RTL coding , and ASIC development . The ideal candidate will have extensive experience in designing, developing, and optimizing high-performance ASICs, with a strong focus on SystemVerilog or VHDL . This role will involve...

ASIC Design EngineerWe are seeking a skilled ASIC Design Engineer with a solid background in digital design, RTL coding, and ASIC development. The ideal candidate will have extensive experience in designing, developing, and optimizing high-performance ASICs, with a strong focus on SystemVerilog or VHDL. This role will involve taking designs from concept to...

Key job responsibilities: As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test...

Key job responsibilities: As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test...

RTL Design: Design and implement RTL code for ASICs in Verilog or SystemVerilog. Create high-quality, reusable, and maintainable RTL code for complex digital systems. Architecture Design: Work closely with architects to understand the high-level design specifications and translate them into efficient RTL code. Participate in defining micro-architecture for...

Job Title: ASIC Design Layout EngineerWe are seeking an experienced ASIC Design Layout Engineer to join our team. The successful candidate will be responsible for the top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing...

Senior ASIC/SoC RTL Engineer/Lead (IP RTL design targeted for SOC, Static checks, some basic protocols) Exp - 4 - 20 Location :Bengaluru, Hyderabad, Pune, Noida, Kochi Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog In depth knowledge on RTL quality checks...

Senior ASIC/SoC RTL Engineer/Lead (IP RTL design targeted for SOC, Static checks, some basic protocols)Exp - 4 - 20Location :Bengaluru, Hyderabad, Pune, Noida, KochiExpertise in SoC subsystem/IP designExpertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System VerilogIn depth knowledge on RTL quality checks (Lint, CDC)Knowledge...

Job Title: Lead DFT EngineerExperience: 7+ Years Location: Bangalore Employment Type: Full-time Industry: Semiconductors / ASIC / SoC DesignJob Summary:We are looking for a Lead DFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with...

Job Title :DFT Engineer/Senior Engineer/ Lead Engineer/DFT Architect Experience : 4years to 12yrs Location : Bangalore, Hyderabad, Kochi, Pune Key Responsibilities: - Interface with ASIC design teams to ensure DFT design rules and coverages are met. - Generate high-quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models...