Tessolve | STA Engineer

2 days ago


india Tessolve Full time

Hi,I am excited to announce that #Tessolve is hiring for Experienced #STA Engineers to join our dynamic team in #Bangalore


Expertise in handling timing closure of complex GPU designs, DDR designs with advanced

technology nodes like 5nm 4nm.

● Expertise in Block level Timing Analysis and timing convergence methodologies across corners

which includes sanity checks, constraint development, timing ECO generation.

● Responsible for internal timing and SOC interface timing closure right from P1 phase till MTO for

high-performance designs.

● Hands-on experience in constraint analysis/ validation/ Top to Block level timing correlation.

● Good understanding of library, derates, AOCV/POCV, multimode multi corner analysis and

intricate dependency on timing analysis.

● Expertise on ECO generation and fixing using Tempus ECO,Tweaker, Powerwizz, DMSA, PTECO

and manually which are leakage aware to achieve faster turnround time of timing closure in

multimillion gate design.

● Hands-on TCL scripting

Imp : Looking for minimum 5 tape out in signoff clouser.


Experience : 4+ Yrs

Notice : ASAP

Location : Bangalore



  • india Tessolve Full time

    Hi,I am excited to announce that #Tessolve is hiring for Experienced #STA Engineers to join our dynamic team in #Bangalore! Expertise in handling timing closure of complex GPU designs, DDR designs with advanced technology nodes like 5nm 4nm. ● Expertise in Block level Timing Analysis and timing convergence methodologies across corners which includes sanity...


  • india Tessolve Full time

    Hi,I am excited to announce that #Tessolve is hiring for Experienced #STA Engineers to join our dynamic team in #Bangalore! Expertise in handling timing closure of complex GPU designs, DDR designs with advanced technology nodes like 5nm 4nm. ● Expertise in Block level Timing Analysis and timing convergence methodologies across corners which includes sanity...


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