Hardware Engineer

1 month ago


india UST Full time

SoC Level-Static Timing Analysis

  • 6+years of relevant experience.
  • Candidate should have strong STA fundamentals.
  • Has done timing sign-off including timing margin calculations independently on SoC Level.
  • Experience in handling STA of multi-power domain/designs.
  • STA flow enhancement, abstraction and bottleneck identification.
  • proficient in design margins and SDC constructs.
  • TAT reduction in multi-mode, multi-power domain/designs.
  • Generate timing ECOs for physical design.
  • Drive ambitious schedules and enables dependent teams to accomplish.
  • Proficient with EDA tools from Cadence/Synopsys.
  • Excellent analytical and communication skills.
  • Show ability to Collaborate in a multi-functional environment ,cross-time or cross-site zone.
  • Proficient in TCL and Perl or other scripting languages is a plus.


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