High-Speed Interface PHY IP Digital Design

Client of Connectpro Exp-6+yrs exp To be part of a highly skilled and challenging high speed parallel # PHY such as # DDR, #LPDDR etc design team. Design and develop high speed interface PHY and its sub-block such as high speed data paths, analog calibration, training, IP initialization, low power control, test, loopback etc Responsible for various...

Front-End implementation of SERDES high speed Interface PHY designs RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules. Work with functional verification team on test-plan development and debug. Develop timing constraints, deliver synthesized netlist to physical design team, and provide...

Front-End implementation of SERDES high speed Interface PHY designsRTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules.Work with functional verification team on test-plan development and debug.Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints...

Client of ConnectproExp-6+yrs expTo be part of a highly skilled and challenging high speed parallel #PHY such as #DDR, #LPDDR etc design team.Design and develop high speed interface PHY and its sub-block such as high speed data paths, analog calibration, training, IP initialization, low power control, test, loopback etcResponsible for various aspects of...

Client of Connectpro Exp-6+yrs exp To be part of a highly skilled and challenging high speed parallel #PHY such as #DDR, #LPDDR etc design team. Design and develop high speed interface PHY and its sub-block such as high speed data paths, analog calibration, training, IP initialization, low power control, test, loopback etc Responsible for various aspects...

Responsibilities Front-End implementation of SERDES high speed Interface PHY designs RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules. Work with functional verification team on test-plan development and debug. Develop timing constraints, deliver synthesized netlist to physical design team, and provide...

ResponsibilitiesFront-End implementation of SERDES high speed Interface PHY designsRTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules.Work with functional verification team on test-plan development and debug.Develop timing constraints, deliver synthesized netlist to physical design team, and provide...

ResponsibilitiesFront-End implementation of SERDES high speed Interface PHY designsRTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules.Work with functional verification team on test-plan development and debug.Develop timing constraints, deliver synthesized netlist to physical design team, and provide...

Responsibilities Front-End implementation of SERDES high speed Interface PHY designs RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules. Work with functional verification team on test-plan development and debug. Develop timing constraints, deliver synthesized netlist to physical design team, and...

Responsibilities Front-End implementation of SERDES high speed Interface PHY designs RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules. Work with functional verification team on test-plan development and debug. Develop timing constraints, deliver synthesized netlist to physical design team, and...

ResponsibilitiesFront-End implementation of SERDES high speed Interface PHY designsRTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules.Work with functional verification team on test-plan development and debug.Develop timing constraints, deliver synthesized netlist to physical design team, and provide...

Responsibilities Front-End implementation of SERDES high speed Interface PHY designs RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules. Work with functional verification team on test-plan development and debug. Develop timing constraints, deliver synthesized netlist to physical design team, and provide...

Senior Memory PHY architect Location: Bangalore We enable tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking,...

Share CV on pathan.khan@wipreo.com JD: Analog IP Lead 1) 15+years of experience in entire Analog IP development including circuit design, layout, AMS verification and characterization 2) Must have led the entire Analog IP development cycle and team 3) Circuit Design implementation of IPs including LDOs, Band Gap reference, Current Generators, POR, ADC/DACs,...

Senior Memory PHY architect Location: Bangalore We enable tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking,...

Senior Memory PHY architectLocation: Bangalore We enable tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking,...

Senior Memory PHY architect Location: Bangalore We enable tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking,...

Our Client is MNC, selected candidates will be on the roles of client, they looking for RTL Design Engineer, RTL Design/Lead Engineer Job Description Job Summary: We are looking for talented RTL Engineers and Leads with expertise in High-speed IPs and CPUs. The ideal candidate will have over 4 years and above experience in uArch design, RTL coding,...

Share CV on JD: Analog IP Lead 1) 15+years of experience in entire Analog IP development including circuit design, layout, AMS verification and characterization 2) Must have led the entire Analog IP development cycle and team 3) Circuit Design implementation of IPs including LDOs, Band Gap reference, Current Generators, POR, ADC/DACs, PLLs, Oscillators,...

Share CV on pathan.khan@wipreo.comJD: Analog IP Lead1) 15+years of experience in entire Analog IP development including circuit design, layout, AMS verification and characterization2) Must have led the entire Analog IP development cycle and team3) Circuit Design implementation of IPs including LDOs, Band Gap reference, Current Generators, POR, ADC/DACs,...