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High-Speed Interface PHY IP Digital Design
2 months ago
RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules.
Work with functional verification team on test-plan development and debug.
Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA.
UPF writing, power aware equivalence checks and low power checks.
DFT insertion and ATPG analysis for optimal SAF, TDF coverage.
Provide support to SoC integration and chip level pre/post-silicon debug.
Skills & Experience
MTech/BTech in EE/CS with hardware engineering experience of 8+ years.
Experience in micro-architecture development, RTL design , front-end flows (# Lint, CDC , low-power checks, etc.), # synthesis/DFT/FV/STA.
Experience with high-speed interface design and good understanding of Industry standard protocols like #USB/PCIe/MIPI, etc. is desirable.
Experience with post-silicon bring-up and debug is a plus.
Able to work with teams across the globe and possess good communication skills.
