NOC/IP-Design Verification Lead Engineer

Exp: 8+ Years Location: Bangalore JD: Key Responsibilities: · Develop UVM-based verification environments for NoC/IP blocks such as FlexNoC, GNOC, or custom NoC fabrics. · Define and implement test plans, coverage models, scoreboards, monitors, and checkers for coherent and non-coherent traffic. · Integrate and verify IPs like AXI4, CHI-B/C/E,...

Exp: 8+ YearsLocation: BangaloreJD:Key Responsibilities:· Develop UVM-based verification environments for NoC/IP blocks such as FlexNoC, GNOC, or custom NoC fabrics.· Define and implement test plans, coverage models, scoreboards, monitors, and checkers for coherent and non-coherent traffic.· Integrate and verify IPs like AXI4, CHI-B/C/E, PCIe, and UCIe...

Exp: 8+ YearsLocation: BangaloreJD:Key Responsibilities:· Develop UVM-based verification environments for NoC/IP blocks such as FlexNoC, GNOC, or custom NoC fabrics.· Define and implement test plans, coverage models, scoreboards, monitors, and checkers for coherent and non-coherent traffic.· Integrate and verify IPs like AXI4, CHI-B/C/E, PCIe, and UCIe...

NoC Verification Engineer Experience : 7 to 14 Years Key Responsibilities: Develop UVM-based verification environments for NoC/IP blocks such as FlexNoC, GNOC, or custom NoC fabrics. Define and implement test plans, coverage models, scoreboards, monitors, and checkers for coherent and non-coherent traffic. Integrate and verify IPs like...

NoC Verification EngineerExperience: 7 to 14 YearsKey Responsibilities:🔸Develop UVM-based verification environments for NoC/IP blocks such as FlexNoC, GNOC, or custom NoC fabrics.🔸Define and implement test plans, coverage models, scoreboards, monitors, and checkers for coherent and non-coherent traffic.🔸Integrate and verify IPs like AXI4, CHI-B/C/E,...

Job Title :IP Verification Engineer – UVM verification Exp Level:4+ yrs Location:Bangalore/Hyderabad Job Description:System Verilog based UVM Functional verification, Behavioral modelling of functional blocks. System level performance verification, traffic patterns, bandwidth & latency analysis. Expertise in AXI4 bus protocol. Experience in Network...

Job Title:IP Verification Engineer – UVM verificationExp Level:4+ yrsLocation:Bangalore/HyderabadJob Description:System Verilog based UVM Functional verification, Behavioral modelling of functional blocks. System level performance verification, traffic patterns, bandwidth & latency analysis. Expertise in AXI4 bus protocol. Experience in Network On Chip...

BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.5+ years of Design Verification experience with SV/UVMStrong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.Design Verification experience verifying complex designs and...

Verification Lead Engineer Join the India team of most cutting-edge and well-funded storage startup in Silicon Valley as the Lead Verification Engineer taking on IP and SoC level verification challenges. As a Verification Lead with a focus on verification of Multi-core, complex, high performance ASIC, you will work to understand the internal...

Verification Lead EngineerJoin the India team of most cutting-edge and well-funded storage startup in Silicon Valley as the Lead Verification Engineer taking on IP and SoC level verification challenges.As a Verification Lead with a focus on verification of Multi-core, complex, high performance ASIC, you will work to understand the internal requirements and...