
NOC/IP-Design Verification Lead Engineer
7 days ago
Exp: 8+ Years Location: Bangalore JD: Key Responsibilities: · Develop UVM-based verification environments for NoC/IP blocks such as FlexNoC, GNOC, or custom NoC fabrics. · Define and implement test plans, coverage models, scoreboards, monitors, and checkers for coherent and non-coherent traffic. · Integrate and verify IPs like AXI4, CHI-B/C/E, PCIe, and UCIe connected via NoC. · Model and validate credit-based flow control, packet routing, QoS, and virtual channel behavior. · Perform assertion-based verification (SVA/DVL) for protocol compliance and corner cases. · Debug complex interactions at simulation or emulation level, including deadlocks, congestion, or ordering violations. · Work closely with architects and RTL teams to align verification coverage and performance metrics. · Perform coverage closure (code + functional) and ensure complete verification sign-off. Required Skills: · Strong experience with SystemVerilog, UVM, and object-oriented testbench development. · In-depth knowledge of NoC protocols (AXI4, CHI, TileLink, or proprietary NoC). · Verification experience with coherent interconnects, cacheable traffic, and memory subsystem validation. · Familiarity with Synopsys, Cadence, or Siemens verification tools (VCS/Xcelium/Questa). · Familiarity with formal verification, assertions (SVA/PSL), and coverage metrics. · Ability to debug low-level issues using waveform analysis, scoreboards, and transactors. · Familiarity with multi-core CPU, DSP, or GPU interconnect systems is a plus.
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NOC/IP-Design Verification Lead Engineer
2 weeks ago
Bangalore Urban, Karnataka, India, IN ACL Digital Full timeExp: 8+ YearsLocation: BangaloreJD:Key Responsibilities:· Develop UVM-based verification environments for NoC/IP blocks such as FlexNoC, GNOC, or custom NoC fabrics.· Define and implement test plans, coverage models, scoreboards, monitors, and checkers for coherent and non-coherent traffic.· Integrate and verify IPs like AXI4, CHI-B/C/E, PCIe, and UCIe...
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NOC/IP-Design Verification Lead Engineer
1 week ago
Bangalore, India ACL Digital Full timeExp: 8+ Years Location: Bangalore JD: Key Responsibilities: · Develop UVM-based verification environments for NoC/IP blocks such as FlexNoC, GNOC, or custom NoC fabrics. · Define and implement test plans, coverage models, scoreboards, monitors, and checkers for coherent and non-coherent traffic. · Integrate and verify IPs like AXI4, CHI-B/C/E, PCIe, and...
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NOC/IP-Design Verification Lead Engineer
1 week ago
bangalore, India ACL Digital Full timeExp: 8+ YearsLocation: BangaloreJD:Key Responsibilities:· Develop UVM-based verification environments for NoC/IP blocks such as FlexNoC, GNOC, or custom NoC fabrics.· Define and implement test plans, coverage models, scoreboards, monitors, and checkers for coherent and non-coherent traffic.· Integrate and verify IPs like AXI4, CHI-B/C/E, PCIe, and UCIe...
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NoC Verification Engineer
1 week ago
Bangalore, India ACL Digital Full timeNoC Verification Engineer Experience : 7 to 14 Years Key Responsibilities: Develop UVM-based verification environments for NoC/IP blocks such as FlexNoC, GNOC, or custom NoC fabrics. Define and implement test plans, coverage models, scoreboards, monitors, and checkers for coherent and non-coherent traffic. Integrate and verify IPs like AXI4, CHI-B/C/E, PCIe,...
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NoC Verification Engineer
1 week ago
bangalore, India ACL Digital Full timeNoC Verification EngineerExperience: 7 to 14 YearsKey Responsibilities:🔸Develop UVM-based verification environments for NoC/IP blocks such as FlexNoC, GNOC, or custom NoC fabrics.🔸Define and implement test plans, coverage models, scoreboards, monitors, and checkers for coherent and non-coherent traffic.🔸Integrate and verify IPs like AXI4, CHI-B/C/E,...
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IP Verification Engineer
1 week ago
Bangalore, India ACL Digital Full timeJob Title :IP Verification Engineer – UVM verification Exp Level:4+ yrs Location:Bangalore/Hyderabad Job Description:System Verilog based UVM Functional verification, Behavioral modelling of functional blocks. System level performance verification, traffic patterns, bandwidth & latency analysis. Expertise in AXI4 bus protocol. Experience in Network On Chip...
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Verification Lead Design Engineer
1 week ago
bangalore, India Cadence System Design and Analysis Full timeBE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.5+ years of Design Verification experience with SV/UVMStrong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.Design Verification experience verifying complex designs and...
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Verification Lead Design Engineer
2 days ago
bangalore, India Cadence System Design and Analysis Full timeBE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer. 5+ years of Design Verification experience with SV/UVM Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must. Design Verification experience verifying complex designs...
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IP Verification Engineer
1 week ago
Bangalore, India Tessolve Full timeJob Title: Senior IP Verification Engineer Experience: 5+ Years Locations: Bengaluru / Hyderabad Company: Tessolve Semiconductor Job Type: Full-Time About Tessolve: Tessolve is a leading engineering solutions provider in the semiconductor space, offering end-to-end services in VLSI design, embedded systems, post-silicon validation, and test engineering . Our...
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IP Verification Engineer
2 weeks ago
bangalore, India Tessolve Full timeJob Title: Senior IP Verification EngineerExperience: 5+ Years Locations: Bengaluru / Hyderabad Company: Tessolve Semiconductor Job Type: Full-TimeAbout Tessolve:Tessolve is a leading engineering solutions provider in the semiconductor space, offering end-to-end services in VLSI design, embedded systems, post-silicon validation, and test engineering. Our...