IP / SoC RTL Senior / Lead Design Engineer
3 weeks ago
This role is for an IP / SoC RTL Senior / Lead Design Engineer to be responsible for the development and integration of IP and sub-systems. The ideal candidate will have strong expertise in logic design, RTL coding, and ASIC development, with a focus on creating high-performance, complex digital designs.
Responsibilities
- Responsible for IP / sub-system level micro-architecture development and RTL coding.
- Prepare block/sub-system level timing constraints.
- Integrate IP/sub-system into larger designs.
- Perform basic verification in either an IP verification environment or on an FPGA.
Skills
- Expertise in Verilog is a must.
- Experience in Logic design, micro-architecture, and RTL coding is essential.
- Knowledge of AMBA protocols - AXI, AHB, APB.
- Experience in synthesis and a strong understanding of timing concepts for ASIC development.
- Hands-on experience in multi-clock designs and asynchronous interfaces is a must.
- Experience with tools used in all phases of ASIC development, such as Lint, CDC, and Simulation.
- Knowledge of low power concepts is a plus.
- Experience in designing controllers for complex protocols like DDR, USB, or PCIe is a plus.
Qualifications
- B.Tech. or M.Tech. with relevant experience.
- Immediate availability is preferred
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