Senior SoC RTL Design Engineer

4 weeks ago

Hyderabad, Telangana, India INDIGLOBE IT SOLUTIONS PRIVATE LIMITED Full time

About the Role :


We are seeking a highly skilled Senior SoC RTL Design Engineer to join our silicon design team. In this role, you will lead the RTL design and micro-architecture development of complex SoC (System-on-Chip) components for cutting-edge semiconductor products.

You will be responsible for driving architecture discussions, writing and reviewing RTL code, collaborating across teams, and ensuring design quality through synthesis and verification stages.

This is a key technical role requiring strong digital design fundamentals, hands-on RTL development experience, and a deep understanding of SoC architectures and subsystems.

Key Responsibilities :


- Define micro-architecture and develop high-quality RTL for SoC subsystems using Verilog/SystemVerilog.

- Own IP/SoC-level RTL development from spec to integration, ensuring performance, area, and power goals are met.

- Work closely with architecture, verification, synthesis, physical design, firmware, and validation teams.

- Perform lint, CDC, and synthesis constraints clean-up, and drive logic equivalence checks (LEC).

- Review specifications and contribute to architectural and micro-architectural decisions.

- Optimize and debug designs for functional correctness, timing, and area/power efficiency.

- Support post-silicon bring-up and validation teams in reproducing and debugging issues.

- Drive design reviews, documentation, and technical decision-making processes.

Required Qualifications :


- Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field.

- Minimum 7+ years of industry experience in RTL design for SoCs or complex ASICs.

- Strong expertise in Verilog/SystemVerilog RTL coding and logic design principles.

- Solid understanding of SoC architecture including buses (AXI, AHB, APB), interconnects, memory subsystems, and peripherals.

- Experience with IP integration and SoC-level design flows.

- Proficiency with industry-standard tools such as Synopsys or Cadence for RTL simulation, linting, CDC, and synthesis.

- Experience in writing synthesis and timing constraints (SDC).

- Good understanding of DFT/DFD, power-aware design, and clock-domain crossing.

Preferred Qualifications :


- Experience with low-power design techniques (UPF/CPF).

- Familiarity with hardware-software co-design and firmware interaction.

- Exposure to FPGA prototyping and emulation platforms.

- Knowledge of system-level modeling (SystemC) is a plus.

- Previous experience mentoring junior engineers or leading design efforts is desirable

(ref:hirist.tech)

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