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Synthesis Design Engineer
2 weeks ago
Work on 4nm/3nm sub-micron Technologies
Synthesis of the Top level and Block level
Co-work with RTL and DFT engineers, prepare SoC Top/Block level constraints
Develop Floor-planning and CTS guidelines for layout.
Working experience with Physical Design will be an added advantage.
Verify timing constraints with Time Vision.
Analyze pre-layout and post-layout timing, generate Timing and Power ECOs, work closely with layout engineers to achieve full chip timing closure
Perform in-house quality check before P&R and after P&R.
Power domain checks for Block and Top, CLP
Job Requirement
8+ years working experience with top/block level Synthesis, Timing closure (STA), Physical Design feedbacks.
Good experience using PrimeTime , Designcompiler and Genus.
Good understanding of Deep Sub Micron topics
Well versed with TCL / Perl script
Experience handling UPF and Conformal Low Power checks
Ability to communicate effectively with multiple global cross-functional teams
Enthusiastic and ability to be an independent player and work in teams
Experience with SoC top design, floorplan, task tracking is a plus
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Synthesis Design Engineer
2 weeks ago
Bangalore City, India MediaTek Full timeJob description:Work on 4nm/3nm sub-micron TechnologiesSynthesis of the Top level and Block level Co-work with RTL and DFT engineers, prepare SoC Top/Block level constraintsDevelop Floor-planning and CTS guidelines for layout. Working experience with Physical Design will be an added advantage.Verify timing constraints with Time Vision.Analyze pre-layout and...
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Synthesis Design Engineer
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Bangalore City, India MediaTek Full timeJob description:Work on 4nm/3nm sub-micron TechnologiesSynthesis of the Top level and Block level Co-work with RTL and DFT engineers, prepare SoC Top/Block level constraintsDevelop Floor-planning and CTS guidelines for layout. Working experience with Physical Design will be an added advantage.Verify timing constraints with Time Vision.Analyze pre-layout and...
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