Synthesis Design Engineer

Job description:Work on 4nm/3nm sub-micron TechnologiesSynthesis of the Top level and Block levelCo-work with RTL and DFT engineers, prepare SoC Top/Block level constraintsDevelop Floor-planning and CTS guidelines for layout.Working experience with Physical Design will be an added advantage.Verify timing constraints with Time Vision.Analyze pre-layout and...

SoC Integration lead Enphase is looking for experienced SoC design engineers with SoC Logic Integration, Synthesis & STA closure experience to join our team in Bangalore India. The team is working on development of our next generation Control ASIC to production in 22nm technology. The ASIC will be a Mixed Signal SOC built around ARM microcontrollers. ...

3+ years experience in STA/SynthesisHand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis.Hands-on experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analysis.Hands-on the DMSA flow to fix pre and post STA timing.Knowledge on the Timing closure on Sub system level & Block level and Chip...

Key Skills : STA, Synthesis, Pnr, sign offAs a Physical Design Engineer at our company, you will play a crucial role in the design and implementation of advanced semiconductor products. You will be responsible for transforming logic designs into physical layouts that meet performance, area, and power targets. Your work will directly impact the success of our...

Key Skills : STA, Synthesis, Pnr, sign offAs a Physical Design Engineer at our company, you will play a crucial role in the design and implementation of advanced semiconductor products. You will be responsible for transforming logic designs into physical layouts that meet performance, area, and power targets. Your work will directly impact the success of our...

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in handling complex data path oriented Multi-million gate synthesis. Working Knowledge on Physical synthesis using tools like Genus, Fusion Compiler Experience in developing constraints...

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world...

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world...

Be part of the Cadence High-Speed SerDes PHY IP Front end Design team responsible for --Defining microarchitecture of digital blocks involving microcontroller-based designs to meet specifications, optimized for performance metrics of timing, area, and power.-Lead and also hands-on end-to-end ASIC design including RTL implementation and design processes of...

Our client is a fabless semiconductor company innovating high performance IC products for IoT Radios, Timing and Portable Audio markets. Founded in 2010 by engineers having extensive global semiconductor product development experience, and is located in Bangalore, India.- They are looking for Senior / Digital Design Engineer to be based at Bangalore with the...

Our client is a fabless semiconductor company innovating high performance IC products for IoT Radios, Timing and Portable Audio markets. Founded in 2010 by engineers having extensive global semiconductor product development experience, and is located in Bangalore, India.- They are looking for Senior / Digital Design Engineer to be based at Bangalore with the...

Job Description Design Enablement team at India, is part of Technology Development group, having charter to develop methodology for advance process nodes, providing opportunity, to be among the first one to work on latest technology. This role, in Design Enablement, is for experienced Individual contributor for Physical design, using Synthesis...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Design and implement DFT IP w/ Verilog/SystemVerilog and/or VHDL - Design and implement RTL for DFT IP incl. POST, IST - Develop synthesis automation for DFT IP including synthesis and timing constraints, RTL insertion and...

Below are the open positions!!!STA : 4+ YearsExperience in chiptop / Top Level / Block level / Fullchip /#Tweaker #Tempus#Primetime#PDN / #IR_Drop / #EMIR : 3+ Yrs> Voltas, Redhawk_SC, EMIR, Power integrityPhysical Design: 4+ YrsExperience in Block level / Full chip /Top Level#Innovus #ICC2Synthesis: 3+ Yrs.Experience in Core Synthesis#Genus #Fusion...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. · This role requires close interaction with multiple cross functional teams across geographies to align on project receivables/deliverables. · Mentoring junior engineers and driving innovation/automation. · BE/B.Tech/M.E/M.Tech...

RTL Design Engineers / Leads / Managers Experience: ~3 to 18+ YearsLocations: India, Hyd, Delhi (NCR), Chennai, Bangalore, Kerala, Ahmedabad, Pune, Mumbai, Etc).Job Description: Expertise in SoC/IP design.Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog.In depth knowledge on RTL quality checks (Lint,...

Minimum 4-8 years Experience in Physical Design engineeringExperience serving as Lead physical design engineer or SOC or block coordinator or top level integrator in TSMC 12m process and beyond requiredExperience running Synthesis-to-GDS ready flows, advanced timing flows and power-driven PD flows (e.g., multi-domain designs with a UPF/CPF flow) , Strong...

Minimum 5-10 years Experience in Physical Design engineeringExperience serving as Lead physical design engineer or SOC or block coordinator or top level integrator in TSMC 12m process and beyond requiredExperience running Synthesis-to-GDS ready flows, advanced timing flows and power-driven PD flows (e.g., multi-domain designs with a UPF/CPF flow) , Strong...

Qualifications: Bachelors’ OR Masters’ degree in Electronics Engineering or equivalent .Experience : 8 to 15 years of relevant experienceJob role:We are looking for Graphics processing Unit (GPU IP) Physical Design expert who has expertise in one or more of following:Clock construction in multi clock designs.High instance design like >2.5M .Meeting...

Minimum 5-10 years Experience in Physical Design engineering Experience serving as Lead physical design engineer or SOC or block coordinator or top level integrator in TSMC 12m process and beyond required Experience running Synthesis-to-GDS ready flows, advanced timing flows and power-driven PD flows (e.g., multi-domain designs with a UPF/CPF flow) , Strong...