Sta Synthesis Engineer

#Urgent_Opening_for_Canvendor #Hiring : Synthesis Engineer (5-10 years) | Bangalore| Immediate Joiners Preferred Location: Bangalore, India Experience: 5-10 years Notice period: Immediate #Key_Requirements : Perform RTL synthesis using tools like Synopsys Design Compiler, Fusion Compiler, or Cadence Genus. Develop and validate timing constraints (SDC) for...

Location- Bangalore/ Noida/ Hyderabad 4+ years experience in STA/Synthesis Hand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis. Synthesis Quality with FE Inputs, LEC environment, UPF Cleanup, Generic Partition level UPF ? and VCLP Signoff. USER mode SDC (will have generic dft constraints), Generic DFT SDC, GCA, Flat Timing...

Location- Bangalore/ Noida/ Hyderabad 4+ years experience in STA/Synthesis Hand-on Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis. Synthesis Quality with FE Inputs, LEC environment, UPF Cleanup, Generic Partition level UPF ? and VCLP Signoff. USER mode SDC (will have generic dft constraints), Generic DFT SDC, GCA, Flat Timing...

Write and implement block level and top-level constraints for Synthesis Static Timing Analysis In your new role you will Implement high-performance low-power and area-efficient digital designs Write and implement block level and top-level constraints for Synthesis Static Timing Analysis Optimize designs for power performance and area and meet PPA goals Power...

Job Title: Static Timing Analysis (STA) EngineerJob OverviewWe are looking for a highly skilled Static Timing Analysis (STA) Engineer to join our ASIC/SoC design team. The ideal candidate will be responsible for performing timing analysis, developing constraints, and driving timing closure across multiple design stages. This role requires strong technical...

Job Title: Static Timing Analysis (STA) Engineer Job Overview We are looking for a highly skilled Static Timing Analysis (STA) Engineer to join our ASIC/SoC design team. The ideal candidate will be responsible for performing timing analysis, developing constraints, and driving timing closure across multiple design stages. This role requires strong technical...

• SoC/Blocks Synthesis/STA methodology & flow for meeting PPA goals• Work with Backend team in realizing PPA goals during PnR & IP & SoC Design team in optimizing the design to meet PPA goals.• Feedback on design issues & solutions. Required Candidate profile• Exp in front end design implementation.• Design flows like Synthesis, Constraint Devel.,...

L&T Technology is looking to hire for STA Engineers. Job Location : Bangalore Detailed JD is below ::JD For STA Engineer-6+ ’ experience • Good knowledge of timing closure knowledge for high frequency timing, congestion, and area sensitive designs. • Can work closely with FE team for constraints development and constraints cleanup. • Work with...

L&T Technology is looking to hire for STA Engineers. Job Location : Bangalore Detailed JD is below :: JD For STA Engineer-6+ ’ experience • Good knowledge of timing closure knowledge for high frequency timing, congestion, and area sensitive designs. • Can work closely with FE team for constraints development and constraints cleanup. • Work with...

BE /BtechEXp- 5- 12 YrsWork on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm.• Take ownership of one or more physical design blocks includes all of, floorplan, CTS, PNR, QRC, STA, PV & IR.• Contribute to design methodology, flow automation.• Innovate & implement Power, Performance and Area optimization...