Design Verification Engineer

3 weeks ago


bangalore, India BITSILICA Full time

Job description

Role & responsibilities

  • 5 Years Experience As a Design Verification Engineer
  • Experience in IP/Subsystem/SOC ASIC Verification.
  • Hands-on expertise in working on Test Plans and test bench development.
  • Expertise in writing test cases, simulation and debugging.
  • Experience building a Verification Environment from scratch using System-Verilog and methodologies like UVM / OVM.
  • Experience in developing Test Plans and Test Cases
  • Expertise in Coverage verification, Function coverage & Code coverage analysis
  • Hands-on work experience on any of PCIe/Eth/USB/DDR/AXI etc .
  • Experience in Assertion Based Verification (ABV).
  • Experience with One Or more simulators from the major EDA suppliers (Cadence, Mentor Or Synopsys)
  • Good Software Skills In Object Oriented Programming (OOP), C, C++, Perl, TCL.
  • Good knowledge of Digital Design, Verilog and System Verilog.


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