Senior Physical Design Engineer

Physical Design Engineer - Senior / Lead Job Description: Strong background in digital IC design, including floorplanning, placement, routing, clock tree synthesis, and optimization. Tools Expertise: Proficient in Innovus, ICC2, and Fusion Compiler for place and route, timing closure, and physical design sign-off. Physical Design: Experience in...

Senior / Lead Physical Design Engineer - EMIR Job Description: Good understanding of IR/Power-Domain-Network signoff at SOC & block level. Experience in RHSC tool. Good at scripting – python. Must have knowledge of Physical Implementation (Synthesis and Place & Route). Effective communication. Strong analytical and problem solving abilities. EMIR signoff...

Job Role:We are seeking a seasoned expert in physical design to assume a leadership position within our organization.Key Responsibilities:Create detailed physical designs from RTL/Netlist to GDSII, ensuring seamless integration and optimal performance.Ensure the successful completion of physical, timing & power signoff at the block level.Develop and...

Technical Requirements- Excellent problem-solving, leadership, and communication skills. Ability to work in a fast-paced environment and lead a cross-functional team.- In-depth knowledge of floor planning, power planning, PNR and signoff checks- Strong experience in static timing analysis (STA), timing closure, and signal integrity.- Expertise in power...

Technical Requirements Excellent problem-solving, leadership, and communication skills. Ability to work in a fast-paced environment and lead a cross-functional team. In-depth knowledge of floor planning, power planning, PNR and signoff checks Strong experience in static timing analysis (STA), timing closure, and signal integrity. Expertise in power...

Responsibilities: Top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Worked on 65nm or lower node...

He/She should be able to do block level / top-level floor planning, PG Planning, partitioning(for hierarchical designs),placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks,...

and RequirementsAt Synopsys we re at the heart of the innovations that change the way we work and play Self-driving cars Artificial Intelligence The cloud 5G The Internet of Things These breakthroughs are ushering in the Era of Smart Everything And we re powering it all with the world s most advanced technologies for chip design and software...

EMIR Engineers Experience : 3years Location : Hyderabad Experience in ASIC EMIR/PD flow and EDA tools experience such as Redhawk-SC , Redhawk – IR and EM Analysis tool Analyze EMIR violations and provide implementation choices to Physical design Scripting language experience: Python, perl, shell preferred. Strong verbal and written...

Jod Discription:Experience ; 4 yearsLocation : HyderabadPosition : EMIR/ PDN EngineersGood understanding of IR/Power-Domain-Network signoff at SOC & block level- Experience in RHSC tool- Good at scripting – python- Must have knowledge of Physical Implementation (Synthesis and Place&Route)- Effective communicationStrong analytical and problem solving...