Senior Physical Design Engineer

1 day ago

Hyderabad, Telangana, India ACL Digital Full time

Technical Requirements

  • Excellent problem-solving, leadership, and communication skills. Ability to work in a fast-paced environment and lead a cross-functional team.
  • In-depth knowledge of floor planning, power planning, PNR and signoff checks
  • Strong experience in static timing analysis (STA), timing closure, and signal integrity.
  • Expertise in power optimization techniques, Upf, including clock gating and multi-voltage domain design
  • Proficiency in physical design tools, such as Synopsys ICC2, Primetime, Calibre, Redhawk-SC
  • Scripting skills in Tcl, Python, or Perl to enhance automation and streamline physical design tasks.
  • Familiarity with DRC, LVS, and other physical verification processes.

Responsibilities

  • Own the physical design implementation of SoC subsystems, including floor planning, placement, clock tree synthesis (CTS), routing, and optimization to meet PPA goals.
  • Work closely with RTL, DFT and IP teams to ensure seamless subsystem integration and resolve physical design issues that impact overall system performance.
  • Collaborate with the Full Chip physical verification team to resolve DRC, LVS, and antenna rule violations, ensuring compliance with top level
  • Lead clock tree synthesis, manage clock skew, insertion delay, and ensure timing closure across all corners and modes. Address timing violations and signal integrity issues.
  • Implement power-saving techniques, such as power gating, multi-voltage domains, and clock gating, to achieve low-power targets while maintaining performance.
  • Develop and optimize custom scripts in Tcl, Perl, or Python to streamline physical design tasks and improve workflow efficiency.
  • Mentor and guide junior physical design engineers, sharing best practices and providing technical guidance to improve team efficiency and expertise.

Experience: 4+ Years

Job Location: Bangalore

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