Design And Verification Engineer
1 month ago
Hiring Design and Verification Engineers Experience: 5-15 years Location: Kochi/Ahmedabad/Bangalore/Vizag · Design verification of IP-level, SoC level and/or block-level/sub-system-level designs · Experience in developing verification plan/verification methodology/flows from scratch · Hands-on expertise with UMV (or similar) methodology, and Verilog/System Verilog (SV) · Experience in constraint-random verification and/or transaction-based verification · Experience in developing one or more of monitors, sequencers, drivers, scoreboards, checkers, coverage analysis/metrics, coverage closure, assertions, VIP components etc. · Experience in one or more of the IPs like LPDDR-4& Above, PCIE-Gen3&Above, SATA, USB 3.0& Above, Ethernet, DDR, NVMe, SDMM, MIPI etc. · Experience with on-chip protocols like AXI/AXI-Lite, AMBA/AHB/APB etc. · Can understand clocking, reset architecture and data flows. Has knowledge of SoC bring-up, bus protocol, register and address map Verification · Experience with gate-level simulations timing/no-timing, SDF annotation · Experience in low-power verification using UPF/CPF power intent flows is a plus · Strong scripting skills with C/C++/Perl/Python · Understanding of emulations platforms, S/W co-development, end-to-end verification EDA Tools: Industry standard tools from Synopsys, Cadence, Mentor etc. Please share your profile to for further discussion.
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