Opportunities for Design Verification-Senior Engineer/Lead/Manager
4 weeks ago
Job Overview: We are seeking an experienced Design Verification Engineer with a minimum 4 years of hands-on experience. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System On Chip designs.
Key Responsibilities:
Hands on verification experience in SOC Design Verification/IP Verification/Sub System Verification/SV-UVM for complex projects, ensuring the successful execution of verification plans.
Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, UCIe, Ethernet, CXL, MIPI, DDR and HBM
Conduct Gate-level simulations, and power-aware verification using Xprop and UPF.
Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams.
Ensure verification signoff criteria are met and documentation is comprehensive.
Experience with verification tools from Synopsys and Cadence, including VCS and Xsim.
Integration of third-party VIPs (Verification IP) from Synopsys and Cadence.
Minimum Qualifications:
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field. OR
Master's degree in Computer Science, Electrical/Electronics Engineering, or related field.
4+ years of hands-on experience in SOC Design Verification/IP Verification/Sub System Verification/SV-UVM for complex projects.
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