Senior Physical Design Engineer

Responsibilities :  Develop and support automated physical design (PD) CAD flows, including floorplanning, placement, and routing optimization.  Customize and optimize physical design flows using industry-standard EDA tools (such as Synopsys ICC2, Cadence Innovus).  Collaborate with the design and CAD teams to improve PD workflows,...

Responsibilities :  Minimum 8+ years of experience and with 0 - 30 Notice period  Perform Synthesis, floorplanning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs.  Define and drive physical design strategies to meet aggressive performance, power, and area targets.  Perform efficient Clock planning and...

Responsibilities :  Minimum 8+ years of experience and with 0 - 30 Notice period  Perform Synthesis, floorplanning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs.  Define and drive physical design strategies to meet aggressive performance, power, and area targets.  Perform efficient Clock planning and...

Responsibilities : Minimum 8+ years of experience and with 0 - 30 Notice period Perform Synthesis, floorplanning, placement, Clock, routing, and PPA optimization for HighSpeed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and areatargets. Perform efficient Clock planning and distribution to...

Responsibilities :  Minimum 8+ years of experience and with 0 - 30 Notice period  Perform Synthesis, floorplanning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs.  Define and drive physical design strategies to meet aggressive performance, power, and area targets.  Perform efficient Clock planning and...

Responsibilities:  Minimum 8+ years of experience and with 0 - 30 Notice period  Perform Synthesis, floorplanning, placement, Clock, routing, and PPA optimization for HighSpeed Advance ASICs.  Define and drive physical design strategies to meet aggressive performance, power, and areatargets.  Perform efficient Clock planning and distribution to...

Minimum 15+ Years of experience SoC Physical Design. Skills – have working experience in advanced FinFET node designs 7nm/5nm/3nm. Experience with Cadence/Synopsys PnR/STA tools and Calibre; good scripting/automation skills is a must. This position is for a senior-level physical design engineer who will work on Floor planning/Bump Planning/ Pin...

Job Role: Physical Design Engineer- Senior/Lead Location: Bangalore, Hyderabad, Noida and Ahmedabad Experience Required: 5+ ROLE & RESPONSIBILITIES Engineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal...

Deep understanding of the concepts related to synthesis, placement & route, CTS, timingconvergence, IR/EM checks and signoff DRC/LVS closure.● Responsible for independent planning and execution of all aspects of physical designincluding floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction,Timing closure, Power and Signal...

Role : Physical Design Engineer ( Physical Verification) Experience Level : 5 to 8 yrs This position is for a senior-level physical verification engineer who will work on Physical verification of a complex SOC/Cores/Blocks DRC, LVS, ERC, ESD, DFM, Tapeout Work hands-on to solve critical design and execution issues related to physical verification and...

LTTS is hiring for Physical Design Engineers with 5+ Years of experience. Job Location : Bangalore, IndiaJob description is as below ::Top 5 Required Skills/Mandatory skills 1. Synthesis 2. Constraints Management 3. Logic Equivalence Check 4. CLP 5. STA Required Education: Bachelor's degree in Computer Science, Electrical/Electronics Engineering,...

LTTS is hiring for Physical Design Engineers with 5+ Years of experience. Job Location : Bangalore, India Job description is as below :: Top 5 Required Skills/Mandatory skills 1. Synthesis 2. Constraints Management 3. Logic Equivalence Check 4. CLP 5. STA Required Education: Bachelor's degree in Computer Science, Electrical/Electronics...

Minimum 15+ Years of experience So C Physical Design. Skills – have working experience in advanced Fin FET node designs 7nm/5nm/3nm. Experience with Cadence/Synopsys Pn R/STA tools and Calibre; good scripting/automation skills is a must. This position is for a senior-level physical design engineer who will work on Floor planning/Bump Planning/ Pin...

Senior Physical Design Engineer: Exp-6+yrs KEY RESPONSIBILITIES: Lead the team responsible for Synthesis, Physical Design, timing and Physical closure Manage a large team of internal and external resources Responsible for ensuring the completion of the SOC chip on schedule with high QOR Physical implementation of block level and subsystem level Contribute...

Senior Physical Design Engineer: Exp-6+yrs KEY RESPONSIBILITIES: Lead the team responsible for Synthesis, Physical Design, timing and Physical closure Manage a large team of internal and external resources Responsible for ensuring the completion of the SOC chip on schedule with high QOR Physical implementation of block level and subsystem level ...

Senior Physical Design Engineer: Exp-6+yrs KEY RESPONSIBILITIES: Lead the team responsible for Synthesis, Physical Design, timing and Physical closure Manage a large team of internal and external resources Responsible for ensuring the completion of the SOC chip on schedule with high QOR Physical implementation of block level and subsystem...

Job Role: Physical Design Engineer- Senior/LeadLocation: Bangalore, Hyderabad, Noida and AhmedabadExperience Required: 5+ROLE & RESPONSIBILITIESEngineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power...

Job Role: Physical Design Engineer- Senior/LeadLocation: Bangalore, Hyderabad, Noida and AhmedabadExperience Required: 5+ROLE & RESPONSIBILITIESEngineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power...

Role : Physical Design Engineer ( Physical Verification)Experience Level : 5 to 8 yrsThis position is for a senior-level physical verification engineer who will work on Physical verification of a complex SOC/Cores/Blocks DRC, LVS, ERC, ESD, DFM, Tapeout Work hands-on to solve critical design and execution issues related to physical verification and sign-off....

Minimum 15+ Years of experience SoC Physical Design.Skills – have working experience in advanced FinFET node designs 7nm/5nm/3nm.Experience with Cadence/Synopsys PnR/STA tools and Calibre; good scripting/automation skills is a must.This position is for a senior-level physical design engineer who will work on Floor planning/Bump Planning/ Pin assignments...