Physical Design Engineer

2 months ago


Bangalore, India L&T Semiconductor Technologies Full time

Role : Physical Design Engineer ( Physical Verification) Experience Level : 5 to 8 yrs This position is for a senior-level physical verification engineer who will work on Physical verification of a complex SOC/Cores/Blocks DRC, LVS, ERC, ESD, DFM, Tapeout Work hands-on to solve critical design and execution issues related to physical verification and sign-off. Own physical verification and sign-off flows, methodologies and execution of SoC/IP/Blocks. Expertise : EDA Tools: Mentor (Calibre), Synopsys (ICV)/ Cadence (Pegasus) Physical verification of SoC/Full-chip-level/Block-level DRC, Experience and understanding of all phases of the IC design process from RTL-> GDS2 LVS, ERC/PERC, DFM, OPC, Tapeout process Developing sign-off methodology/flow to and supporting a larger team Debugging LVS issues at chip-level with complex analog-mixed signal IPs Design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.) Preferably worked on 5nm/7nm/12nm/14nm/16nm/22nm nodes at the major foundries Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full-chip components Good understanding of CMOS/FinFET process and circuit design, base layer related DRCs, ERC rules, latch-up etc. Experience with ERC rules, PERC rules, ESD rules has an added advantage Strong communication skills, problem solving and analytical skills



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