ASIC Design Verification

6 days ago

New Delhi, India L&T Technology Services Full time

Job Description DV Positions:Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verificationDevelop functional tests based on verification test planDrive Design Verification to closure based on defined verification metrics on test plan, functional and code coverageDebug, root-cause and resolve functional failures in the design, partnering with the Design teamQualifications and Skills for DV Positions:Bachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologiesExperience in development of UVM based verification environments from scratchExperience in architecting and implementing Design Verification infrastructure and executing the full verification cycleExperience with verification of ARM/RISC-V based CPU sub-stems or SoCsExperience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, EthernetExperience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environmentsExperience with revision control stems like Mercurial(Hg), Git or SVN

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