Physical Verification Engineer

4 days ago


New Delhi, India ACL Digital Full time

Physical Verification EngineersExperience : 3 years Location : Bangalore Will be responsible for Runing Physical verification analysis for multiple designs, analyzing results and providing fixes to address the issues for complex cpu designs, in latest technology nodes. n (LVS, DRC, ERC, PERC, Antenna, DFM) at block and top levels. Collaborate with Physical Design (PD), RTL, and CAD teams to resolve PV issues and ensure sign-off quality. Analyze and debug PV violations using Calibre tool and provide fixes to be taken using PnR tools like Innovus Understanding of all Physical verification signoff checks Understanding of DRC/LVS/ANTENNA for latest technology nodes and solving the issues Basic Scripting in TCL/SHELL/... Good communication skill for explaining issues/solutions Good skill for working with team Interested,please drop your updated CV to janagaradha.n@acldigital.com



  • New Delhi, India LeadSoc Technologies Pvt Ltd Full time

    Physical Verification Engineer Job DescriptionWork with various implementation team to drive full-chip Physical Verification Sign-off closure in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out. Co-work with Place & Route team to resolve full-chip layout integration issues. Work with various implementation team to drive Physical Verification...


  • New Delhi, India ACL Digital Full time

    Physical Verification Engineers Experience : 2-5 years Location : BangaloreJob Description – Physical Verification EngineerKey ResponsibilitiesPerform physical verification for SoCs, cores, and block-level designs. Run and debug DRC (Design Rule Check), LVS (Layout vs. Schematic), ERC (Electrical Rule Check), Antenna checks, and DFM (Design for...


  • New Delhi, India LeadSoc Technologies Pvt Ltd Full time

    Physical Verification Engineer Job DescriptionWork with various implementation team to drive full-chip Physical Verification Sign-off closure in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out. Co-work with Place & Route team to resolve full-chip layout integration issues. Work with various implementation team to drive Physical Verification...


  • New Delhi, India LeadSoc Technologies Pvt Ltd Full time

    Physical Verification EngineerJob DescriptionWork with various implementation team to drive full-chip Physical Verification Sign-off closure in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out. Co-work with Place & Route team to resolve full-chip layout integration issues. Work with various implementation team to drive Physical Verification...


  • New Delhi, India LeadSoc Technologies Pvt Ltd Full time

    Physical Verification EngineerJob DescriptionWork with various implementation team to drive full-chip Physical Verification Sign-off closure in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out. Co-work with Place & Route team to resolve full-chip layout integration issues. Work with various implementation team to drive Physical Verification...


  • New Delhi, India LeadSoc Technologies Pvt Ltd Full time

    Physical Verification EngineerJob DescriptionWork with various implementation team to drive full-chip Physical Verification Sign-off closure in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out. Co-work with Place & Route team to resolve full-chip layout integration issues. Work with various implementation team to drive Physical Verification...


  • New Delhi, India ACL Digital Full time

    Physical Verification EngineersExperience : 3 years Location : Bangalore Will be responsible for Runing Physical verification analysis for multiple designs, analyzing results and providing fixes to address the issues for complex cpu designs, in latest technology nodes. n (LVS, DRC, ERC, PERC, Antenna, DFM) at block and top levels. Collaborate with Physical...

  • Physical Design

    2 days ago


    New Delhi, India L&T Semiconductor Technologies Full time

    Role : Sr Physical Design Lead/BE IntegrationThis position is for senior level engineer Full Chip Physical Design/Integrations/ SoC Floor planning/Bump Planning/ Pin Assignments /Feed through/ LFU Optimization/Physical Verification, Power design/implementation/signoff. He must have hands on Physical Design experience and must have handled RTL to GDS II at...

  • Physical Design

    2 days ago


    New Delhi, India L&T Semiconductor Technologies Full time

    Role : Sr Physical Design Lead/BE IntegrationThis position is for senior level engineer Full Chip Physical Design/Integrations/ SoC Floor planning/Bump Planning/ Pin Assignments /Feed through/ LFU Optimization/Physical Verification, Power design/implementation/signoff. He must have hands on Physical Design experience and must have handled RTL to GDS II at...

  • Physical Design

    11 hours ago


    New Delhi, India L&T Semiconductor Technologies Full time

    Role : Sr Physical Design Lead/BE Integration This position is for senior level engineer Full Chip Physical Design/Integrations/ SoC Floor planning/Bump Planning/ Pin Assignments /Feed through/ LFU Optimization/Physical Verification, Power design/implementation/signoff. He must have hands on Physical Design experience and must have handled RTL to GDS II at...