Memory Layout Engineer
2 days ago
Job Title:Memory Layout Engineer Experience:3+yrs Location:Bangalore Job Type:Full-time Industry:Semiconductors / VLSI / Memory Design Job Summary: We are looking for aMemory Layout Engineerwith strong expertise in physical layout design of memory components such as SRAM, ROM, Register Files, or custom memory IPs. The candidate will be responsible for delivering high-quality, DRC/LVS-clean layouts optimized for performance, area, and power. Key Responsibilities: Design full-custom layouts for memory components like SRAM, ROM, CAM, Register Files, or sense amplifiers. Work closely with circuit designers to understand schematics and translate them into optimized layouts. Floorplanning, transistor-level placement, routing, and matching to meet electrical and physical design constraints. Run physical verification (DRC, LVS, ERC, antenna checks) using industry-standard tools. Perform parasitic extraction (PEX) and assist in post-layout simulation. Ensure layouts meet design rules for process technologies (e.g., 5nm, 7nm, 16nm, 28nm). Implement design automation using SKILL, Python, or Tcl where applicable. Work with cross-functional teams (circuit, verification, CAD) to meet project milestones. Required Skills and Experience: B.E/B.Tech or M.E/M.Tech in Electronics or Electrical Engineering. 3 years of hands-on experience in custom layout design, preferably in memory design. Strong understanding of CMOS layout techniques, matching, shielding, and electromigration. Experience with: Tools:Cadence Virtuoso, Calibre DRC/LVS, StarRC, ICC, QRC Technologies:Advanced FinFET and planar nodes (28nm and below) Deep understanding of design rules (DRC), LVS, and physical verification sign-off flows. Excellent attention to detail, layout quality, and debugging skills. Preferred Qualifications: Experience in compiler-based memory generation or memory compilers. Exposure to high-speed or low-power memory layout optimization techniques. Experience working with foundry design kits (PDKs) and tape-out processes. Scripting experience in SKILL or Python for layout automation and checks. Why Join Us? Work on next-generation memory designs for AI, mobile, and high-performance computing chips. Be part of a highly skilled layout team with access to leading-edge nodes and tools. Competitive salary, performance bonuses, and long-term growth opportunities.Interested can share Cv to Sharmila.b@acldigital.com
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Memory Layout Engineer
2 weeks ago
New Delhi, India Exiger Technologies Full timeExperience Level 3 to 8 Years ( Mid-Level Role)Responsibilities: As Memory Layout Engineer, we will work on developing memory compilers layouts and memory Fast Cache instances layouts for our next generation Cores achieving outstanding PPA.Required Skills and Experience :We Prefer graduate or postgraduate from a University or Engineering School, in...
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Memory Layout Engineer
6 days ago
New Delhi, India Exiger Technologies Full timeExperience Level 3 to 8 Years ( Mid-Level Role)Responsibilities:As Memory Layout Engineer, we will work on developing memory compilers layouts and memory Fast Cache instances layouts for our next generation Cores achieving outstanding PPA.Required Skills and Experience :We Prefer graduate or postgraduate from a University or Engineering School, in Electronic...
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Memory Layout Engineer
16 hours ago
New Delhi, India BITSILICA Full timeExp: 3 to 8 YearsLocation: BangaloreNotice: Immediate - 15 days✅ Memory Leafcell layout library design from scratch including top level integration.✅ Good knowledge on different types of memory architectures.✅ Good knowledge in optimized layout design for better performance.✅ Sound knowledge & hands on experience in Finfet technology, layout design...
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Memory Design Engineers
6 days ago
New Delhi, India ACL Digital Full timeJob Title: Memory Design EngineerExperience Required: 2+ YearsLocation: BangaloreJob Type: Full-timeIndustry: Semiconductors / VLSI / Memory IPJob Summary:We are seeking a skilled Memory Design Engineer to join our advanced memory IP development team. The candidate will be responsible for architecting, designing, and validating high-performance and low-power...
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Lead Memory Design Engineer
6 days ago
New Delhi, India ACL Digital Full timeJob Title: Lead Memory Design EngineerExperience: 6+ YearsLocation: BangaloreEmployment Type: Full-timeIndustry: Semiconductors / VLSI / Memory IP / SoCJob Summary:We are looking for an experienced and highly motivated Lead Memory Design Engineer to drive the architecture, design, and development of advanced memory IPs such as SRAMs, ROMs, CAMs, and Register...
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eNVM Bitcell Layout Design Engineer
4 days ago
New Delhi, India Tata Electronics Full timeTata Electronics Private Limited (TEPL) is a greenfield venture of the Tata Group with expertise in manufacturing precision components.Tata Electronics (a wholly owned subsidiary of Tata Sons Pvt. Ltd.) is building India’s first AI-enabled state-of-the-art Semiconductor Foundry. This facility will produce chips for applications such as power management IC,...
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eNVM Bitcell Layout Design Engineer
6 days ago
New Delhi, India Tata Electronics Full timeTata Electronics Private Limited (TEPL) is a greenfield venture of the Tata Group with expertise in manufacturing precision components.Tata Electronics (a wholly owned subsidiary of Tata Sons Pvt. Ltd.) is building India’s first AI-enabled state-of-the-art Semiconductor Foundry. This facility will produce chips for applications such as power management IC,...
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Memory Layout Engineers-Bangalore
4 days ago
New Delhi, India Central Business Solutions Inc. Full timeHi, We are looking for aMemory Layout Engineerfor one of our clients. Experience:4 to 8 Years Job Description: We are seeking experiencedMemory Layout Engineerswith hands-on expertise in3nm or below process nodes . The ideal candidate should have a strong background incustom layout design and verificationfor advanced semiconductor technologies....
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AMS Layout
6 days ago
New Delhi, India ACL Digital Full timeACL Digital is looking for an Experienced Layout EngineerMinumum 4+ years of Experience for Bangalore LocationGood to have ESD BlocksMust have Lower nodes from TSMCAMS/IO Memory - LayoutInterested share/refer karthick.v@acldigital.comBachelor's or Master's Degree with 4 - 12 years of Analog Layout experienceDemonstrated leadership experience of at least 3...
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Senior Memory Design Lead Engineer
6 days ago
New Delhi, India ACL Digital Full timePosition: Senior Memory Design Lead Engineer Location: BangaloreResponsibilities: As Memory Design Engineer, we will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding PPA. Required Skills and Experience : Understanding of computer architecture and concepts. Basic understanding of CMOS...
