RTL Design Engineer-CXL

RTL Design Engineer(CXL)Experience - 5+yrsLocation- BangaloreJDStrong RTL designer with IP design experienceSoC IntegrationInterconnect Generation for a given configurationCXL 3.1 and above design experience

RTL Design Engineer for Interface Controller IP development team.Position is based in Bangalore or Noida.The role would include design and support of the RTL of the PCIe/CXL/IDE/UALink IP solution of Cadence.The work involved will be working with the existing RTL, addition of new features into the RTL, ensuring various customer configurations are clean as...

Hi All,Job Location: Bangalore Notice Period: 15 days to 30 Days Minimum: 5+ Years 1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog. 2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units,...

Hi All,Job Location: Bangalore Notice Period: 15 days to 30 Days Minimum: 5+ Years 1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog. 2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units,...

Job Description Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs Intelligent Connectivity Platform integrates CXL,...

Job Description Hi All, Job Location: Bangalore Notice Period: 15 days to 30 Days Minimum: 5+ Years 1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog. 2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience...

Hi All,Job Location: BangaloreNotice Period: 15 days to 30 DaysMinimum: 5+ Years1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog.2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units,...

Job Location: BangaloreNotice Period: 15 days to 30 DaysMinimum: 5+ Years1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog.2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units, Floating point...

Principal RTL Design Engineer & ArchitectBangaloreWe are seeking a seasoned RTL Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in leading state of the RTL designs involving solutions for automotive camera and display systems.Responsibilities• Design and develop microarchitectures for a...

We are seeking a highly experienced SoC Architecture & RTL Engineer to design, implement, and optimize complex digital systems for next-generation computing platforms. This role offers the opportunity to work on cutting-edge SoC architectures involving high-speed interfaces and industry-standard protocols. Key Responsibilities Design and develop SoC...