Memory Design Engineers
4 weeks ago
Job Title:Memory Design Engineer Experience Required:2+ Years Location:Bangalore Job Type:Full-time Industry:Semiconductors / VLSI / Memory IP Job Summary: We are seeking a skilledMemory Design Engineerto join our advanced memory IP development team. The candidate will be responsible for architecting, designing, and validating high-performance and low-power memory blocks (e.g., SRAM, ROM, Register Files) for use in SoCs and ASICs across leading-edge process technologies. Key Responsibilities: Design custom memory circuits such as SRAM, ROM, CAM, Register Files, or eFuse. Work closely with layout, verification, and technology teams to ensure optimal performance, power, and area (PPA). Perform transistor-level circuit design, simulation, and optimization for speed, power, and robustness. Analyze and simulate key circuits: sense amplifiers, bitline pre-charge, wordline drivers, decoders, write drivers, etc. Run simulations across PVT corners using tools like HSPICE, Spectre, or XA. Collaborate with layout teams for floorplanning and to ensure DRC/LVS clean layouts. Perform post-layout simulations and analysis (IR drop, EM, aging). Participate in memory characterization, yield improvement, and silicon bring-up support. Contribute to memory compiler development (if applicable). Required Skills and Experience: B.E/B.Tech or M.E/M.Tech in Electronics, Electrical Engineering, or VLSI. 2+ years of experience in full custom memory design. Strong background in analog/mixed-signal CMOS circuit design. Proficiency in simulation tools: HSPICE, Spectre, FastSPICE, XA. Experience with design in advanced nodes (e.g., 28nm, 16nm, 7nm, 5nm, FinFET). Familiarity with ESD, IR drop, EM, and reliability analysis techniques. Understanding of process variation and Monte Carlo simulations. Good debugging, problem-solving, and documentation skills. Preferred Qualifications: Experience with memory compiler architecture/design. Knowledge of radiation-hardened memory (RHBD) or safety-compliant memory (ISO 26262). Scripting knowledge (e.g., Python, Perl, Tcl) for automation. Exposure to silicon bring-up and correlation to simulation results.Interested can share Cv to Sharmila.b@acldigital.com
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Memory Design Engineer
3 weeks ago
New Delhi, India ACL Digital Full timePosition: Senior Memory Design Engineer Location: Bangalore / NoidaResponsibilities: As Memory Design Engineer, we will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding PPA. Required Skills and Experience : Understanding of computer architecture and concepts. Basic understanding of CMOS...
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Lead Memory Design Engineer
2 weeks ago
New Delhi, India ACL Digital Full timeJob Title:Lead Memory Design Engineer Experience:6+ Years Location:Bangalore Employment Type:Full-time Industry:Semiconductors / VLSI / Memory IP / SoC Job Summary: We are looking for an experienced and highly motivatedLead Memory Design Engineerto drive the architecture, design, and development of advanced memory IPs such as SRAMs, ROMs, CAMs, and Register...
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Memory Design Engineer
4 weeks ago
New Delhi, India ACL Digital Full timeThe ideal candidate will be responsible for executing and leading the full design process from ideation to production.During the creation process, you will ensure that our designs meeting all necessary design responsibilities.QualificationsBachelor's Degree or equivalent experience in Engineering or relevant technical degree Minimum 2 years of job experience...
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Senior Memory Designer
5 days ago
New Delhi, India Lattice Semiconductor Full timeLattice OverviewThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales,...
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Senior Memory Designer
1 week ago
Delhi, India Lattice Semiconductors Full timeLattice OverviewThere is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales,...
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Senior Memory Designer
1 week ago
Delhi, India Lattice Semiconductors Full timeLattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales,...
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Memory Layout Engineer
1 week ago
New Delhi, India Capgemini Engineering Full timeRole: Memory/Custom Layout EngineerExperience: 3 to 12 YearsLocation: BengaluruJob Description:- 3-8 years of experience in Memory/Custom Layout design. - Memory Leafcell layout library design from scratch including top level integration. - Good knowledge on different types of memory architectures. - Good knowledge in optimized layout design for better...
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Memory Layout Engineer
4 weeks ago
New Delhi, India BITSILICA Full timeExp: 3 to 8 YearsLocation: BangaloreNotice: Immediate - 15 days✅ Memory Leafcell layout library design from scratch including top level integration.✅ Good knowledge on different types of memory architectures.✅ Good knowledge in optimized layout design for better performance.✅ Sound knowledge & hands on experience in Finfet technology, layout design...
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Sr Principal PD Design Engineer
1 week ago
New Delhi, India Cadence System Design and Analysis Full timeThis is a full-time on-site role for a Sr Principal Physical Design Engineer based in Bengaluru. The engineer will be responsible for overseeing and contributing to the physical design process of complex IPs, especially Memory IPs with higher frequencies on latest Tech. nodes. Day-to-day tasks include floorplanning, placement, clock tree synthesis, routing,...
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Sr Principal PD Design Engineer
5 days ago
New Delhi, India Cadence System Design and Analysis Full timeThis is a full-time on-site role for a Sr Principal Physical Design Engineer based in Bengaluru. The engineer will be responsible for overseeing and contributing to the physical design process of complex IPs, especially Memory IPs with higher frequencies on latest Tech. nodes. Day-to-day tasks include floorplanning, placement, clock tree synthesis, routing,...
