STA Engineer

22 hours ago


New Delhi, India Mirafra Technologies Full time

Exp 5-8Yrs relevant Location- GermanyDeliverables and Results: Timing and power Signoff data Digital timing and power sign-off guidelines Reports, analysis and scripts (perl/python) to improve MethodologyRequirements: A sound knowledge in digital chip design including timing, power and IR drop analysis and verification as well as functional simulation Deep knowledge in Static Timing Analysis Preliminary knowledge in SPICE simulation Programming skills in Perl/ Python Experience on Digital Implementation flow and STA (Cadence/Synopsys) Experience on IR Drop/EM verification as a plus An independent and self-responsible working style with active share of knowledgePrior Knowledge: Experienced STA user with background of used timing related Methodologies (Synopsys/Cadence implementation + STA Tools) Experience on IR Drop/EM verification as a plus (Ansys Redhawk(SC)/ Cadence Voltus or Ansys Totem) Scripting knowledge (Perl or Python and tcl)Language Skills: English proficiency German being a plus


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