Physical Verification Engineer
3 weeks ago
Physical Verification EngineerExperience: 2 to 5 YearsLocation: BangaloreNotice Period: ImmediateJob DescriptionKey Responsibilities:- Perform Physical Verification checks including DRC, LVS, ERC, and Antenna checks at block and full-chip level. - Work with foundry rule decks (TSMC / Samsung / GF / Intel / UMC etc.) to ensure design sign-off compliance. - Debug and resolve layout violations by working closely with the Physical Design, Layout, and Circuit teams. - Run Parasitic Extraction (PEX) and support timing and SI closure teams for accurate model generation. - Perform DFM checks and assist with design enhancements for manufacturability. - Support tape-out preparation, validation, reports, checklists, and documentation.Required Skills & Expertise:- Strong working experience with Calibre / PVS / ICV for DRC & LVS sign-off. - Understanding of CMOS layout fundamentals, standard cells, macros, and routing architectures. - Familiarity with GDS / OASIS data formats, hierarchical layout structures, and physical design flows. - Basic knowledge of STA, IR/EM, PDN, and PnR flows is a plus. - Ability to collaborate in cross-functional teams and drive closure of PV issues.Good to Have:- Experience with advanced technology nodes (7nm / 5nm / 3nm). - Scripting in Tcl, Python, or Shell to automate verification workflows. - Exposure to Custom Layout or Analog/Mixed-signal PV environments.Education:- B.E / B.Tech / M.E / M.Tech in Electronics / VLSI / Electrical / Semiconductor or related domain.
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Physical Verification Engineer
2 weeks ago
New Delhi, India LeadSoc Technologies Pvt Ltd Full timePhysical Verification Engineer Job DescriptionWork with various implementation team to drive full-chip Physical Verification Sign-off closure in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out. Co-work with Place & Route team to resolve full-chip layout integration issues. Work with various implementation team to drive Physical Verification...
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Physical verification engineers
4 weeks ago
New Delhi, India ACL Digital Full timePhysical Verification Engineers Experience : 2-5 years Location : BangaloreJob Description – Physical Verification EngineerKey ResponsibilitiesPerform physical verification for SoCs, cores, and block-level designs. Run and debug DRC (Design Rule Check), LVS (Layout vs. Schematic), ERC (Electrical Rule Check), Antenna checks, and DFM (Design for...
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Physical Verification Engineer
2 weeks ago
New Delhi, India LeadSoc Technologies Pvt Ltd Full timePhysical Verification Engineer Job DescriptionWork with various implementation team to drive full-chip Physical Verification Sign-off closure in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out. Co-work with Place & Route team to resolve full-chip layout integration issues. Work with various implementation team to drive Physical Verification...
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Physical Verification Engineer
2 weeks ago
New Delhi, India LeadSoc Technologies Pvt Ltd Full timePhysical Verification EngineerJob DescriptionWork with various implementation team to drive full-chip Physical Verification Sign-off closure in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out. Co-work with Place & Route team to resolve full-chip layout integration issues. Work with various implementation team to drive Physical Verification...
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Physical Verification Engineer
4 days ago
New Delhi, India LeadSoc Technologies Pvt Ltd Full timePhysical Verification EngineerJob DescriptionWork with various implementation team to drive full-chip Physical Verification Sign-off closure in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out. Co-work with Place & Route team to resolve full-chip layout integration issues. Work with various implementation team to drive Physical Verification...
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Physical Verification Engineer
2 days ago
New Delhi, India LeadSoc Technologies Pvt Ltd Full timePhysical Verification EngineerJob DescriptionWork with various implementation team to drive full-chip Physical Verification Sign-off closure in the area of (DRC, LVS, ANT, ERC, ESD, PERC) for tape-out. Co-work with Place & Route team to resolve full-chip layout integration issues. Work with various implementation team to drive Physical Verification...
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Physical Verification Engineer
2 days ago
New Delhi, India ACL Digital Full timePhysical Verification EngineersExperience : 3 years Location : Bangalore Will be responsible for Runing Physical verification analysis for multiple designs, analyzing results and providing fixes to address the issues for complex cpu designs, in latest technology nodes. n (LVS, DRC, ERC, PERC, Antenna, DFM) at block and top levels. Collaborate with Physical...
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Physical Design
2 days ago
New Delhi, India L&T Semiconductor Technologies Full timeRole : Sr Physical Design Lead/BE IntegrationThis position is for senior level engineer Full Chip Physical Design/Integrations/ SoC Floor planning/Bump Planning/ Pin Assignments /Feed through/ LFU Optimization/Physical Verification, Power design/implementation/signoff. He must have hands on Physical Design experience and must have handled RTL to GDS II at...
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Physical Design
2 days ago
New Delhi, India L&T Semiconductor Technologies Full timeRole : Sr Physical Design Lead/BE IntegrationThis position is for senior level engineer Full Chip Physical Design/Integrations/ SoC Floor planning/Bump Planning/ Pin Assignments /Feed through/ LFU Optimization/Physical Verification, Power design/implementation/signoff. He must have hands on Physical Design experience and must have handled RTL to GDS II at...
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Physical Design
9 hours ago
New Delhi, India L&T Semiconductor Technologies Full timeRole : Sr Physical Design Lead/BE Integration This position is for senior level engineer Full Chip Physical Design/Integrations/ SoC Floor planning/Bump Planning/ Pin Assignments /Feed through/ LFU Optimization/Physical Verification, Power design/implementation/signoff. He must have hands on Physical Design experience and must have handled RTL to GDS II at...
