STA Synthesis Engineer

BE /BtechEXp- 5- 12 YrsWork on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm.• Take ownership of one or more physical design blocks includes all of, floorplan, CTS, PNR, QRC, STA, PV & IR.• Contribute to design methodology, flow automation.• Innovate & implement Power, Performance and Area optimization...

Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis.Job Description In your new role you will:Implement high-performance, low-power, and area-efficient digital designs.Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis .Optimize designs for power, performance, and area,...

Job Summary:We are seeking a skilled STA Engineer with a strong background in Test and DFT architectures. The ideal candidate will have hands-on experience evaluating and writing high-quality timing constraints (SDCs) and performing thorough timing checks across complex digital designs.Key Responsibilities:Analyze and validate timing constraints (SDC) for...

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill...

L&T Technology is looking to hire for STA Engineers. Job Location : Bangalore Detailed JD is below ::JD For STA Engineer-6+ ' experience • Good knowledge of timing closure knowledge for high frequency timing, congestion, and area sensitive designs. • Can work closely with FE team for constraints development and constraints cleanup. • Work with...

Job Title: STA Design Engineer (Backend)Location: BangaloreExperience: 5+ YearsJob Description:We are looking for an experienced STA Design Engineer with strong expertise in Static Timing Analysis (STA) for ASIC/SoC backend design. The candidate should have hands-on experience in timing closure, signoff methodologies, and working closely with physical design...

Experience: 5+yearsLocation: BangaloreJob Description:As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process...

Skills RequiredNetlist and constraint sign in checks and validation.Prime time constraint development at full chip level and clean up.Multimode multi corner timing knowledge and timing closure at sub HM/block/top level.Top level timing closure with sign off STA in MMMC with Xtalk and OCV. Top level ECO implementation strategy development for netlist, RTL and...

Job Summary:We are seeking a skilled STA Engineer with a strong background in Test and DFT architectures. The ideal candidate will have hands-on experience evaluating and writing high-quality timing constraints (SDCs) and performing thorough timing checks across complex digital designs.Key Responsibilities:Analyze and validate timing constraints (SDC) for...

Desired Exp: 5 to 8 YearsJD:Timing analysis, validation and debug across multiple PVT conditions using Tempus.Familiar with Tempus DMMMC flow for STASTA setup, convergence, reviews, and signoff for scan and func.Review of Unconstrained endpoints and check timing reports.Proficient in STA and timing methodologies with good understanding of noise, crosstalk,...