Synthesis (STA) Engineer

2 days ago


Bengaluru, Karnataka, India Canvendor Full time
Urgent_Opening_for_Canvendor
Hiring: Synthesis Engineer (5-10 years) | Bangalore| Immediate Joiners Preferred

Location: Bangalore, India

Experience: 5-10 years

Notice period: Immediate

Key_Requirements:
  • Perform
    RTL synthesis
    using tools like Synopsys Design Compiler, Fusion Compiler, or Cadence Genus.
  • Develop and validate
    timing constraints (SDC)
    for complex designs with multiple clock domains.
  • Execute
    Static Timing Analysis (STA)
    using PrimeTime or Tempus to ensure timing closure across all corners and modes.
  • Identify and resolve
    setup, hold, and transition violations
    through constraint tuning and logic optimization.
  • Conduct
    logic equivalence checks (LEC)
    between RTL and synthesized netlist.
  • Implement
    timing ECOs
    and support final tape-out activities.
  • Collaborate with physical design teams to ensure timing goals are met during PnR.
  • Automate synthesis and STA flows using
    TCL, Perl, or Python
    .
  • Perform
    formal verification
    and quality checks to ensure first-pass success.
  • Optimize designs for
    PPA
    through iterative synthesis and timing analysis.

If interested kindly share your updated CV to


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