Ciliconchip Chief Technology Officer

Ciliconchip Chief Technology Officer

Experience: 20+ Years

Location: Bangalore

Role Overview

The Chief Technology Officer (CTO) will define and lead the company’s technology vision,

architecture, and innovation roadmap in Mixed-Signal Analog IP development, with focus

areas spanning power management, UCIe interfaces, memory, and sensor technologies.

This leadership role will drive R&D excellence, IP innovation, and engineering capability across

global design teams.

Key Responsibilities

1. Technology Strategy & Vision

● Define and own the company’s Mixed-Signal Analog IP technology roadmap, aligning

it with business strategy and market direction.

● Identify emerging analog and mixed-signal trends (UCIe, chiplet integration,

low-power and high-speed analog architectures) that can create competitive

differentiation.

● Establish and nurture strategic partnerships with foundries, EDA vendors, universities,

and ecosystem players to strengthen IP innovation.

● Guide R&D in advanced design methodologies, reusable IP frameworks, and

next-generation process readiness.

2. Engineering Leadership

● Oversee all engineering functions — Analog/Mixed-Signal Design, Circuit

Verification, Layout, Validation, and Integration.

● Set technical standards, design quality metrics, and best practices across all IP

development programs.

● Ensure predictable execution and delivery of high-performance, low-power

Mixed-Signal IPs.

● Drive PPA (Power, Performance, Area) optimization, design reusability, and

automation in design and verification flows.

3. IP Development & Productization

● Drive first-silicon success and productization of advanced Mixed-Signal IPs across

power, UCIe, memory, and sensor domains.

● Architect reusable IP cores, subsystems, and platforms to accelerate future product

and customer integration cycles.

● Oversee technology evaluation for EDA tools, analog/mixed-signal design kits (PDKs),

libraries, and process migrations.

● Review IP specifications to ensure feasibility, scalability, manufacturability, and

compliance with integration standards.

4. Innovation & R&D

● Lead advanced R&D initiatives in emerging domains such as low-power architectures,

high-speed interfaces, and AI-assisted design automation.

● Sponsor internal innovation programs and IP filings, fostering a culture of technical

excellence and experimentation.

● Drive internal architecture forums, design councils, and cross-functional technical

reviews to accelerate learning and innovation.

5. Talent Development & Organization Building

● Mentor and develop senior technical leaders including Directors, Fellows, and

Principal Engineers across analog, mixed-signal, and IP disciplines.

● Foster a high-performance, innovation-driven culture emphasizing accountability and

technical depth.

● Partner with HR to define technical career ladders, learning frameworks, and

university collaboration programs to build a sustainable talent pipeline.

6. Customer & Ecosystem Engagement

● Serve as the company’s technical ambassador with customers, partners, and industry

forums.

● Translate customer requirements into scalable, IP-level technical solutions and

roadmaps.

● Engage in strategic business reviews, co-development initiatives, and customer

engagements to ensure alignment with market needs.

● Represent the company at industry conferences and technology consortia,

showcasing IP leadership and innovation.

7. Governance & Risk Management

● Ensure IP protection, design security, and compliance across all programs.

● Define and enforce technical governance frameworks, including design reviews and

quality audits.

● Mitigate risks through robust validation, simulation coverage, and silicon correlation

strategies.

Qualifications

Minimum Requirements

● B.E./B.Tech/M.Tech/Ph.D. in Electrical, Electronics, or Microelectronics

Engineering.

● 20+ years of experience in Analog/Mixed-Signal IP design and development, with at

least 10 years in senior leadership roles.

● Proven track record of leading large, multi-disciplinary engineering teams across

global sites.

● Deep hands-on expertise in power management circuits, high-speed interfaces

(UCIe), memory IPs, and sensor integration.

● Strong understanding of EDA tool chains, design flows, process technologies, and

silicon manufacturing.

● Demonstrated success in building world-class engineering teams and delivering IP

innovation at scale.