Ciliconchip GM

3 days ago


Bengaluru, Karnataka, India Ciliconchip Circuit Full time ₹ 12,00,000 - ₹ 30,00,000 per year

GM / Vice President Product Development

Location: Bangalore

Experience: 20+ years

Role Overview

The GM / VP of Product Development will lead the end-to-end design, development, and delivery of Mixed-Signal Analog IPs, with a focus on power solutions, UCIe, memory interfaces, and sensor technologies. This leadership role requires deep technical acumen in analog and mixed-signal domains, combined with strategic vision to drive innovation, scalability, and business growth.

Key Responsibilities

Strategic Leadership

  • Define and articulate the Mixed-Signal Analog IP product development strategy, aligning it with business goals, technology roadmaps, and market trends.
  • Drive innovation and differentiation across power management, interface, and sensor IP portfolios.
  • Evaluate emerging technologies and ecosystem trends (such as UCIe, chiplet architectures, and low-power design) to identify new opportunities for IP development.
  • Collaborate with executive leadership to set long-term objectives and investment priorities for the Mixed-Signal IP portfolio.

Product Development & Engineering Execution

  • Lead cross-functional teams in architecture, circuit design, verification, validation, and system integration to deliver high-quality Mixed-Signal Analog IPs.
  • Oversee the complete IP lifecycle, from concept, design, and simulation to validation, silicon characterization, and product qualification.
  • Establish robust engineering processes emphasizing first-time-right silicon, design reuse, and power-performance optimization.
  • Ensure IP design compliance with performance, reliability, manufacturability, and integration requirements.
  • Collaborate with foundry and packaging partners to optimize yield, quality, and production scalability.

Team Leadership & Organizational Development

  • Build, mentor, and lead a high-performing team of analog/mixed-signal design engineers, product managers, and validation experts.
  • Create a culture of technical excellence, collaboration, and innovation across design and development teams.
  • Attract and develop top talent; establish clear competency frameworks and career growth paths.
  • Lead multi-geo teams effectively, driving collaboration between design centers, ecosystem partners, and key customers.

Product Strategy & Market Alignment

  • Translate customer requirements and market insights into actionable IP specifications and technology roadmaps.
  • Partner with business, sales, and customer engineering teams to define IP positioning, go-to-market strategy, and customer engagement models.
  • Prioritize IP development initiatives based on ROI, technical differentiation, and market demand.
  • Engage with strategic customers and partners to ensure roadmap alignment with system-level integration needs.

Operational Excellence & Governance

  • Define and monitor KPIs for IP quality, design efficiency, schedule adherence, and innovation metrics.
  • Implement best practices in Agile/Lean development and design governance for IP programs.
  • Drive continuous improvement through design reviews, silicon feedback loops, and data-driven decision-making.
  • Represent the Product Development organization in executive reviews and board-level discussions.

Required Qualifications

  • Bachelors or Masters degree in Electronics, Electrical Engineering, or related field; Ph.D. preferred.
  • 20+ years of progressive experience in analog/mixed-signal IP development, with at least 10+ years in leadership roles driving IP design, validation, and delivery.
  • Proven success in managing large-scale design teams and cross-functional engineering programs in leading semiconductor or IP companies.
  • Deep technical expertise in analog, power management, high-speed interfaces (UCIe), memory subsystems, and sensor integration.
  • Strong understanding of semiconductor IP lifecycle, EDA tools, and silicon manufacturing flows.
  • Demonstrated ability to build and scale world-class engineering teams and deliver complex IP portfolios to market.

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