Staff - ASIC STA Engineer
1 month ago
Staff - ASIC STA Engineer
Top 10 Semiconductor Organization in the world
Location: Bangalore
Staff - ASIC STA Engineer
Position Description
- The position is part of a Mix-Signal ASIC digital team. The group owns various high-speed IPs (like ONFI & DDR PHY, SerDes) and IO buffer Chips from spec to post silicon characterization.
- Responsible for front end implementation of high speed Mixed Signal IPs and Analog intensive ASICs which includes synthesis, LEC, Low power flows, prelayout STA and postlayout STA/Timing closure
- Collaborate with Design, DV and PD teams to achieve closure.
- Complete quality delivery for synthesis and timing closure
- Mentoring and coaching other design team members on technical issues
- Learns design & technology requirements, develops and customizes flows to achieve all the requirements.
- Equal opportunity position with excellent pay package
SKILLS Required
- Highly experienced in synthesis, LEC, Low Power flows and timing closure
- Proven ability to understand a new mixed signal complex IP with minimal design team help and achieve synthesis to timing closure with 1st time silicon success.
- Handling blocks with complex designs, high frequency clocks and complex clocking
- complete understanding of timing constraints including asynchronous designs and DFT
- Have debug experience to solve issues
- scripting and automation
- Working knowledge of low power designing involving multiple power domains
- Should be able to identify and meet requirements for critical paths of multi-GHz designs
- The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams
- M.S./M.Tech, BS/BE (Electronics)
- Experience Required: 7+ Years
Contact:
Uday
Mulya Technologies
muday_bhaskar@yahoo.com
"Mining The Knowledge Community"
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