RTL Designer
2 weeks ago
Job Title : RTL Designer ASIC (8-13 Years Experience).
Location : Bangalore.
Company : Analog Devices.
Job Summary :
Seeking an experienced RTL Designer with a strong background in ASIC design to join our cutting-edge engineering team. The ideal candidate will have 8 to 13 years of experience in RTL design, with deep expertise in ASIC design methodologies, tools, and workflows.
You will play a pivotal role in the design and development of complex digital circuits, working closely with cross-functional teams to deliver innovative semiconductor solutions.
Key Responsibilities :
- RTL Design : Develop and optimize Register Transfer Level (RTL) code for complex digital circuits, ensuring high performance, low power, and area efficiency.
- ASIC Development : Work on all phases of ASIC design including architecture, microarchitecture, RTL coding, synthesis, and timing closure.
- Verification : Collaborate with verification teams to define verification plans, develop testbenches, and debug RTL using simulation tools.
- Synthesis and STA : Perform logic synthesis and Static Timing Analysis (STA) to ensure the design meets timing, power, and area goals.
- Collaboration : Work closely with system architects, hardware engineers, and software teams to define design specifications and ensure successful integration.
- Documentation : Maintain thorough documentation of design specifications, methodologies, and results to ensure clear communication across teams.
- Mentorship : Provide technical guidance and mentorship to junior engineers, fostering a collaborative and innovative working environment.
Qualifications :
- Education : Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Experience : 8 to 13 years of hands-on experience in RTL design and ASIC development.
Technical Skills :
- Proficiency in RTL design using Verilog/SystemVerilog.
- Strong understanding of digital design fundamentals, including finite state machines, pipelining, and clock domain crossing.
- Experience with ASIC design flow, including synthesis, STA, and formal verification.
- Familiarity with EDA tools such as Synopsys Design Compiler, Mentor Graphics, or Cadence tools.
- Knowledge of low-power design techniques and methodologies.
- Experience with FPGA prototyping and emulation is a plus.
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