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RTL Design Lead
1 week ago
Responsibilities:Work with architecture and physical design teams to code power/area/performance optimized RTL.Participate in verification at block and chip levelRun Lint, CDC/RDC, LEC checksDevelop block and chip level constraints and run synthesis
Qualifications:Bachelor's, Master's, or Ph.D. degree in Electrical Engineering with 12-15 years of industry experienceProficiency in hardware description languages (Verilog, VHDL) and microarchitecture modeling tools (SystemVerilog, SystemC).Experience with SoC design methodologies, including RTL design, synthesis, timing analysis.Ability to self-verify RTL blocks/top level before handing off to the DV team is necessary.Exposure to Analog digital interfaces and physical layer development for standards like ehternet, USB3, MIPI is highly preferred.Exposure to STA, DFT and physical design is highly preferred.Excellent communication and teamwork skills. Should be a self-starter and a highly motivated individual contributor.
Contact:UdayMulya "Mining The Knowledge Community"
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