Technologist, ASIC Development Engineering

5 months ago

Bengaluru, India Western Digital Full time
Job Description

Job Summary:

We are seeking an experienced STA Architect to lead our technical team. The ideal candidate will have extensive experience in Static Timing Analysis, a deep understanding of digital design, and the ability to lead and mentor a team of engineers.

This role requires hands-on expertise in STA tools, methodologies, and a strategic vision to drive the timing closure of complex designs.

 

Key Responsibilities:

- Lead the STA function and oversee all aspects of timing analysis and closure for ASIC designs.

- Develop and implement STA methodologies and best practices to ensure high-quality design closure.

- Collaborate with cross-functional teams, including IP design, DFT,  and verification teams, to address timing challenges and drive design convergence.

- Conduct thorough timing analysis using industry-standard STA tools (e.g., Synopsys PrimeTime, Cadence Tempus).

- Define and drive timing constraints development and validation processes.

- Provide technical leadership and mentorship to junior engineers, fostering a culture of continuous learning and innovation.

- Work closely with project managers to ensure timely delivery of design milestones and project goals.

- Stay updated with the latest industry trends and advancements in STA methodologies and tools.

- Participate in design reviews, providing expert insights and recommendations to optimize performance and timing.

- Troubleshoot and resolve complex timing issues, utilizing advanced debugging techniques.


Qualifications

Qualifications:

- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.

- Minimum of 15 years of experience in Static Timing Analysis, with a proven track record of successful timing closure on multiple complex designs.

- In-depth knowledge of STA tools such as Synopsys PrimeTime, Cadence Tempus, or similar.

- Strong understanding of digital design principles, including RTL design, synthesis, place and route, and clock tree synthesis.

- Experience with timing constraint development and validation.

- Proficient in scripting languages (e.g., TCL, Perl, Python) for automation of STA tasks.

- Excellent problem-solving skills and the ability to troubleshoot complex timing issues.

- Strong leadership and team management skills, with experience leading and mentoring engineers.

- Effective communication skills, with the ability to articulate complex technical concepts to cross-functional teams.

- Strong organizational skills and the ability to manage multiple tasks and projects simultaneously.

- Experience with advanced process nodes (e.g., 7nm, 5nm) is highly desirable.



Additional Information

Western Digital thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.

Western Digital is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at staffingsupport@wdc.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

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