Staff Engineer – ASIC Digital Design(DDR PHY)
3 months ago
Staff Engineer – ASIC Digital Design(DDR PHY)
Top10 Semiconductor Organization in the World
Bangalore
We are a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Staff Engineer – ASIC Digital Design(DDR PHY)
JOB Description
- To be part of a highly skilled and challenging high speed parallel PHY such as DDR, LPDDR etc design team.
- Design and develop high speed interface PHY and its sub-block such as high speed data paths, analog calibration, training, IP initialization, low power control, test, loopback etc
- Responsible for various aspects of design and verification from spec to silicon along with interface design for controller and SoC.
- Active involvement in problem solving and implementing opportunities for improvement
- Mentoring and coaching other design team members on technical issues
- Pair with Analog designers to ensure smooth interface between Digital and Analog circuits
- Equal opportunity position with excellent pay package
SKILLS Required
- Strong fundamental knowledge of digital design, Verilog and scripting languages
- Experience with micro-architecture and Asynchronous digital designs
- Working knowledge of Synthesis, STA, Lint & CDC
- Working knowledge of DDR/LPDDR JEDEC protocol and DDR PHY designs
- Experience with DDR training algorithms and data path designs
- Experience in domain transfer designs, APB/JTAG, DFI
- M.S./M.Tech, BS/BE (Electronics)
Experience Required: 7+ Years
Contact:
Uday
Mulya Technologies
muday_bhaskar@yahoo.com
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