Design Verification Lead/Manager

Job Description: Design Verification Lead/Manager (10+ Years) – BangaloreWe are seeking an experiencedDesign Verification (DV) Lead/Managerto drive verification strategy, methodology, and execution for complex IP/subsystem/SoC designs. The ideal candidate will bring strong technical depth along with proven leadership capabilities.Key Responsibilities:Lead...

Job Description: Design Verification Lead/Manager (10+ Years) – Bangalore We are seeking an experienced Design Verification (DV) Lead/Manager to drive verification strategy, methodology, and execution for complex IP/subsystem/SoC designs. The ideal candidate will bring strong technical depth along with proven leadership capabilities. Key Responsibilities:...

Job Description: Design Verification Lead/Manager (10+ Years) – Bangalore We are seeking an experienced Design Verification (DV) Lead/Manager to drive verification strategy, methodology, and execution for complex IP/subsystem/SoC designs. The ideal candidate will bring strong technical depth along with proven leadership capabilities. Key Responsibilities:...

· 6+ years of experience in ASIC/SOC/IP Verification using SystemVerilog and UVM/OVM methodologies. · Hands-on in testbench development, coverage closure, and debugging using VCS/Xcelium/Questa. · Strong in protocol verification — DDR, PCIe, USB, SATA, MIPI, Ethernet. · Exposure to CPU-based SoC Verification, including ARM/RISC-V environments and cache...

· 6+ years of experience in ASIC/SOC/IP Verification using SystemVerilog and UVM/OVM methodologies.· Hands-on in testbench development, coverage closure, and debugging using VCS/Xcelium/Questa.· Strong in protocol verification — DDR, PCIe, USB, SATA, MIPI, Ethernet.· Exposure to CPU-based SoC Verification, including ARM/RISC-V environments and cache...

· 6+ years of experience in ASIC/SOC/IP Verification using SystemVerilog and UVM/OVM methodologies. · Hands-on in testbench development, coverage closure, and debugging using VCS/Xcelium/Questa. · Strong in protocol verification — DDR, PCIe, USB, SATA, MIPI, Ethernet. · Exposure to CPU-based SoC Verification , including ARM/RISC-V environments and...

· 6+ years of experience in ASIC/SOC/IP Verification using SystemVerilog and UVM/OVM methodologies.· Hands-on in testbench development, coverage closure, and debugging using VCS/Xcelium/Questa.· Strong in protocol verification — DDR, PCIe, USB, SATA, MIPI, Ethernet.· Exposure to CPU-based SoC Verification, including ARM/RISC-V environments and cache...

·6+ years of experiencein ASIC/SOC/IP Verification usingSystemVerilogandUVM/OVMmethodologies.· Hands-on intestbench development, coverage closure, and debuggingusing VCS/Xcelium/Questa.· Strong inprotocol verification— DDR, PCIe, USB, SATA, MIPI, Ethernet.· Exposure toCPU-based SoC Verification, including ARM/RISC-V environments and cache coherency.·...

We’re Hiring – Lead Design Verification Engineer @ Eximietas Design! Position: Lead Design Verification Engineer Experience: 7+ Years Locations: Bangalore / Ahmedabad / Pune / Hyderabad Key Skills: Proven experience in Design Verification using SystemVerilog and UVM Strong experience in minimum 2 protocols like AXI, AHB, Ethernet, PCIe, UCIe, DDR, USB,...

We’re Hiring – Lead Design Verification Engineer @ Eximietas Design! Position: Lead Design Verification Engineer Experience: 7+ Years Locations: Bangalore / Ahmedabad / Pune / Hyderabad Key Skills: - Proven experience in Design Verification using SystemVerilog and UVM - Strong experience in minimum 2 protocols like AXI, AHB, Ethernet, PCIe, UCIe, DDR,...