tsmc

TSMC 16/12nm,7nm,5nm,3nm and below (other foundries are also fine like Intel, Samsung, GF). Preferably TSMC 5nm/3nm experience. 2. Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. 3. Verification flows - LVS/DRC/DFM/Antenna check/EMIR experience. 4. Responsible for...

TSMC 16/12nm,7nm,5nm,3nm and below (other foundries are also fine like Intel, Samsung, GF). Preferably TSMC 5nm/3nm experience. 2. Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. 3. Verification flows - LVS/DRC/DFM/Antenna check/EMIR experience. 4. Responsible for on-time...

1.TSMC 16/12nm,7nm,5nm,3nm and below (other foundries are also fine like Intel, Samsung, GF). Preferably TSMC 7nm/5nm/3nm experience. 2.Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. Analog blocks like Regulators/Charge pumps/Power Management etc.. 3.Responsible for...

Design analog and high-speed circuits including Transmitter & Receiver equalization (FFE/CTLE/DFE), op-amps, Bandgap references, regulators, charge pumps, ADC, PLL, DLL, CDR and other precision blocks in advanced FinFET process nodes, preferably TSMC 16nm and lower nodes. Conduct simulations across PVT corners, collaborate with layout and verification teams,...

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Role Description • Custom layouts for High-Speed Custom Analog/Digital blocks, such as Ring Oscillators, Dividers, Bias Blocks (Voltage & Current references), pre-drivers etc. in TSMC 2nm & 3nm, • Independent in debugging and resolving the layout fixes in various verification flows • Flexible to take different tasks in project. • Execute tasks with...

Own physical implementation solutioning, methodology definition, PPA strategy, and implementation planning for complex SoCs. Serve as technical authority for physical design architecture and feasibility. Key Responsibilities Actively participating in the customer proposals • Define implementation methodologies for large chips. • Develop floorplanning and...

About the job • Position : Memory Layout Engineer • Experience: 3 to 8 years • Location : Bangalore • Notice Period : 0- 30 days • Role: • Layout Design of SRAM/CAM/RF custom/compiler memories in TSMC A14/2FF/3FF technologies or Samsung SS8/SS2 technologies. • Responsibilities: • Develop key building blocks of memory architecture, such as...

Role Description UST Job Title: Associate III - VLSI At UST, we help the world’s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in over 25 countries, we build for boundless impact—touching billions...

Design analog and high-speed circuits including Transmitter & Receiver equalization (FFE/CTLE/DFE), op-amps, Bandgap references, regulators, charge pumps, ADC, PLL, DLL, CDR and other precision blocks in advanced FinFET process nodes, preferably TSMC 16nm and lower nodes. Conduct simulations across PVT corners, collaborate with layout and verification teams,...

SMTS Physical Design Engineer Location: Bengaluru, India Experience: 5–10 Years Technology Nodes: TSMC 3nm / 2nm EDA Tool: Cadence Innovus Role Overview We are seeking a highly skilled SMTS Physical Design Engineer with strong expertise in physical design sign-off and advanced-node implementation. The ideal candidate will have hands-on experience with...

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Technical Ownership • Lead...

Analog Layout Engineer | 4–10 YearsCompany: LeadIC Design Pvt Ltd Employment Type: Full-time Workplace Type: Hybrid Location: Bengaluru,Pune, Hyderabad Experience: 4–8 years Notice Period: Immediate to 30 days only About the RoleLeadIC Design is looking for experienced Analog Layout Engineers with strong expertise in full-custom analog and mixed-signal...

Job Details:Job Description: We are seeking a highly motivated Senior CAD Engineer for CPU IP Design Planning Methodology and Automation to support, maintain, enhance, and deploy Design Planning and RTL to Floorplan methodologies for next generation CPU IP development. The successful candidate will work closely with CPU Physical Design, Architecture,...

Job Details:Job Description: We are seeking a highly experienced and motivated Senior Technical Lead - CPU Physical Design to lead the physical implementation of next-generation CPU IPs from floorplanning through signoff. The successful candidate will provide technical leadership across the physical design lifecycle, driving PPA optimization, execution...

About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate,...

Physical Design (PD) Lead Location: Bangalore, India |Company: LTSCT — L&T Semiconductor Technologies Limited Reporting To: Chandra — Senior Architect, DC HW Systems | Experience: 10+ years (mandatory) Role Summary The Physical Design Lead owns the loop from architecture to silicon realization for the full xPU SiP. You will drive floorplanning,...

Job Details: Job Description: We are seeking a highly experienced and motivated Senior Technical Lead - CPU Physical Design to lead the physical implementation of next-generation CPU IPs from floorplanning through signoff. The successful candidate will provide technical leadership across the physical design lifecycle, driving PPA optimization, execution...