perl developer jobs in Mumbai

Lead STA & Synthesis Engineer Location: Bengaluru Experience: 8–12 Years Role Overview We are looking for a Lead STA & Synthesis Engineer with strong hands-on expertise in Static Timing Analysis, RTL Synthesis, timing closure, and implementation flows for complex SoC designs. Key Responsibilities Own RTL-to-gate synthesis and timing analysis for...

4-10 years of experience in emulation model development and verification for complex SoCs. Substantial knowledge of emulation platforms from Synopsys, Cadence, and Siemens. Strong understanding of processor architecture, SoC components, and interconnect protocols. Hands-on experience with IO protocols such as PCIe, CXL, Ethernet, and memory technologies like...

LTTS is looking for DV engineers with 7+ years of experience for lead role...detailed JD is below mentioned. 8/10+ of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification 8/ 10+ experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM based methodologies Experience in development of UVM based...

AMS Verification Engineer Experience: 3 to 5 Years Location: Bangalore Job Description Perform Analog Mixed-Signal (AMS) verification using SystemVerilog, Wreal, and Verilog-AMS for IP and subsystem-level designs. Develop and maintain mixed-signal testbenches , behavioral and real-number models (RNM) for analog/digital interfaces. Drive functional...

Www. Encharge Location : Bangalore-Hybrid / 2 days to work/3 days home/Remote-any where in India Staff/Senior Staff Physical Design Floorplan & PDN Lead Bangalore En Charge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. En Charge’s robust and scalable next-generation in-memory computing technology provides...

Formal Verification Engineer Experience : 4 to 12 Years Location : Bangalore Job Description Responsible for developing and executing formal verification strategies for IP and SoC blocks. Write and prove assertions using SystemVerilog Assertions (SVA) or PSL. Use tools like JasperGold, VC Formal, or OneSpin to verify complex designs. Collaborate with...

Job Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve...

Job Summary: We are looking for a talented and experienced RTL Design Engineer to join our team and play a key role in the design and development of next-generation ASICs/SoCs. You will be responsible for all aspects of RTL design, from concept to RTL coding, verification, and integration. Responsibilities: Develop RTL code for complex digital circuits using...

Company : Esconet Technologies Location : Delhi/NCR – Okhla Phase 1, New Delhi (On-site) Experience : 5+ Years About the Role Esconet Technologies is looking for a highly motivated HPC System Integrator/Administrator with a strong passion for cluster administration, system integration, and validation of HPC clusters. In this role, you will influence the...

LTTS is hiring for Design Verification Engineers with 5+ Years of experience. Job Location : Bangalore, India Detailed JD is as below :: Job Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification Develop functional tests based on verification test plan Drive...

L&T Technology services is looking to hire for Design Verification Engineers for Lead Role. Job Location : Bangalore Experience : 7-10 YearsJob details are as below :: Job Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification Develop functional tests based on...

About the RoleJoin a cutting-edge hardware development team to push the boundaries of Machine Learning by designing the Register-Transfer Level (RTL) for custom AI accelerators. You will co-design microarchitectures and write high-quality RTL code, shaping the next generation of computing infrastructure.Core ResponsibilitiesMicroarchitecture & Design: Define...

Static Timing Analysis (STA) Lead Join the India team of most cutting-edge and well-funded storage startup in Silicon Valley as the Lead STA Engineer working on timing closure of complex high performance ASIC in latest technology nodes. As a STA lead you will be working on PrimeTime based flow development and timing closure of multi-million gate SoC design...

Senior Design Verification EngineerLocation: Bangalore. Experience: 4 to 10 Years. Notice Period: Any.Perform verification of complex digital designs at block and system level. Develop testbenches using SystemVerilog/UVM for simulation and debugging. Create and execute comprehensive test plans for functional verification. Achieve coverage targets using code...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This role requires close interaction with multiple cross functional teams across geographies to align on project receivables/deliverables. Mentoring junior engineers and driving innovation/automation. BE/B.Tech/M.E/M.Tech with 3+ years of relevant...

Job Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage Debug, root-cause and resolve...

Summary: We are seeking an innovative and highly motivated Digital Design Engineer to develop next-generation MCU and embedded processing platforms while leveraging AI/ML technologies to transform silicon development workflows. The candidate will contribute to RTL design, microarchitecture development, IP integration, and design optimization while utilizing...

Key Responsibilities: Develop and optimize logic design, register transfer level (RTL) coding, and simulation for the CPU. Participate in defining the architecture and microarchitecture features of the CPU design. Write RTL and optimize logic for power, performance, area, and timing goals. Ensure design integrity for physical implementation through effective...

MNC Hiring: Analog Mixed Signal Layout Engineer We are looking for an experienced Analog Mixed Signal Layout Engineer for an exciting opportunity with our MNC client. Location: Hyderabad Work Mode: Onsite (5 days a week) Experience: 5+ years of relevant experience Education: B.E./B.Tech/M.E./M.Tech in Electrical Engineering Mandatory Skills: 5+...

Senior Memory Design Engineer Location: Bengaluru Experience: 5–10 Years Job Type: Full-time Role Overview We are looking for a Senior Memory Design Engineer to drive circuit-level design and optimization of advanced memory macros. The role requires strong expertise in SRAM/Memory circuit design, custom transistor-level design, simulation,...